UC San Diego

Power networks supply power from the P/G pads on a chip to the circuit modules. With the rapid increase of working frequency and continuous scaling of VLSI technology, the power supply network is experiencing unprecedented noise, which causes significant delay variation of devices, or even logic failure. Therefore, robust and reliable power supply network has increasing importance for high-speed circuit performance. In this dissertation, we study the methodologies and algorithms to perform the power networks analysis and optimization. We design an efficient circuit simulation flow based on frequency domain computation, which serves as a helpful tool for analysis and optimization. Then, we explore approaches to make the worst case noise analysis considering clock gating with multiple domains. The worst case voltage drop and violation area are studied in this analysis work. After power network analysis, the optimization is to confine the voltage fluctuation to meet with a target noise tolerance. The power-up sequencing problem and the noise minimization with decoupling capacitors (decap) and controlled-ESRs are studied. In the circuit simulation work, a frequency domain based simulation method is proposed to obtain the time domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial fraction expression, which can be easily converted to time-domain waveform. Numerical results show that the proposed simulation method is up to several hundred times faster than commercial fast simulators, like HSPICE and MSPICE. And, the proposed method is able to analyze large-scale power networks that the commercial tools are not able to afford. The worst case voltage drop and violation area analysis are both studied in a multi- domain clock gated power network. We describe a linear time complexity algorithm to find the worst case voltage drop and the corresponding clock gating pattern. An efficient integer linear programming (ILP) based approach is proposed to find the worst voltage violation area. Leakage current is taken into consideration to accurately estimate the violation noise. The optimization work covers two pars. Firstly, an efficient heuristic algorithm is introduced to arrange the power-up sequence in a multi- domain power network to minimize the noise. Secondly, we propose a sequential quadratic programming (SQP) based algorithm to optimize power network with both decap and controlled-ESR. A revised sensitivity computation is derived to consider both voltage drop and overshoot. Experimental results shows the controlled-ESR reduces the noise by 25% with the same decap budget