UCLA

Direct bonding is a materials integration process in which wafer substrates are directly bonded without any intermediate layers. This technique has been used to fabricate direct bonded n-GaAs//n-GaAs, n-GaAs//n-InP, and n-InP//n-InP structures comprised of combinations of on-axis substrates and substrates with (001) faces misoriented 4° toward <111> in order to study the effect of relative surface misorientation on the electrical properties of the bonded interface. Simulation and measurement of interface electrical conductivity were used to identify properties including height and shape of the potential barrier. Across all substrate combinations, as the relative surface misorientation was increased, the interface resistance and height of the interfacial potential barrier also increased. Current density – voltage measurements of GaAs//InP bonded structures revealed no band structure asymmetry at low ( ± 50 mV) bias. Transmission electron microscopy was used to observe the morphology of the interface between InP//InP and GaAs//InP structures. Consistent with previous reports, results of electrical measurements indicate that the potential barrier height at interfaces containing at least one side InP are less sensitive to increased interface resistance with increasing misorientation.

Low temperature (≤ 600 °C) and kPa applied pressure to initiate bonding between (NH4S)2 pretreated GaAs and InP wafers was used to fabricate direct bonded structures. Wafers were bonded face-to-face on-axis, with relative misorientation of 4° or 8°, or a by bonding a combination of 4° miscut substrates bonded such that relative misorientation was zero. The samples were annealed at 400 °C for 2 hours to strengthen the bond, and then subjected to rapid thermal processing at 600 °C for 2 minutes to improve the electrical conductivity. When compared to on-axis structures, the interface resistance at room temperature for 4° misoriented bonded pairs increased from 0.011 Ω∙cm2 to 2.8 Ω∙cm2 for GaAs//GaAs structures, from 0.00824 Ω∙cm2 to 0.0161 Ω∙cm2 for GaAs//InP structures and only from 0.0063 Ω∙cm2 to 0.0089 Ω∙cm2 for InP//InP structures. The electronic behavior at the interface was modeled using the Seager-Pike theoretical model for electron tunneling between adjacent semiconductor bicrystals. In accordance with this model the zero-bias conductance was used to estimate the conduction barrier height at the bonded interface. The zero-bias conductance taken at temperatures from 90 to 340 K reveals an increase in potential barrier height across all wafer combinations as the degree of surface misorientation is increased, from 0.26 eV to 0.305 eV for InP//InP structures, from 0.32 eV to 0.39 eV for GaAs//InP structures, and from 0.54 eV to 1.0 eV for GaAs//GaAs structures.

For all material combinations studied, structures with zero relative misorientation displayed equivalent electrical performance to nominal on-axis substrates, demonstrating that relative surface misorientation rather than substrate miscut is responsible for changes in electrical resistivity. The large increase in potential barrier height for GaAs//GaAs structures indicates that the degree of relative misorientation between GaAs//GaAs wafer bonded pairs has a significant impact on interface electrical properties, and is consistent with previous GaAs//GaAs studies. However for GaAs//InP wafer bonded pairs, the relative misorientation across the bonded interface plays a less significant role, and the impact of relative misorientation is least significant for InP/.InP bonded structures. This is illustrated by the increase in potential barrier of 0.04 eV for InP//InP structures, 0.06 eV for GaAs//InP structures, and 0.47 eV for GaAs//GaAs structures as relative misorientation is increased from 0° to 8°.

High resolution transmission electron microscopy and high-angle annular dark field are used to confirm the misorientation of GaAs//InP and InP//InP bonded samples and determine the interface morphology. No interfacial layer is present in InP//InP structures before or after rapid thermal processing. It is observed that regions adjacent to the interface undergo a process of atomic redistribution and recrystallize into the same lattice arrangement as the bulk semiconductor. GaAs//InP interfaces are observed to contain regions direct substrate contact with oxide inclusions in between after rapid thermal processing, consistent with previous work on GaAs//GaAs interfaces.

It is concluded that for III-V direct wafer bonded heterostructures, interface conductivity is a function of both the relative misorientation between the (001) surfaces and the material pair. The significance of this study is that the additional variable of lattice mismatch does not degrade electrical conductivity through GaAs//InP interfaces. This is significant for applications where heterostructure interface conduction must be controlled, such as the direct bonding of III-V wafers for photovoltaic applications.