UC Riverside

Electrostatic discharge (ESD) failure is a major reliability problem to integrated circuits (IC). On-chip ESD protection is mandatory for all IC chips to protect against any possible ESD damages. Therefore, Whole-chip ESD protection circuit simulation is essential to chip-level ESD protection design synthesis, optimization, verification and prediction. Today, trial-and-error approaches still dominate in practical ESD circuit designs due to lack of full-chip ESD simulation tools and accurate ESD device modeling technique.

This thesis reports a new chip-level ESD CAD tool, which can accurately extract ESD devices from layout files, generate an ESD netlist, simulate ESD discharge function at chip level and conduct full-chip ESD zapping test simulation. This CAD tool is designed with several unique algorithms and a smart ESD parametric checking mechanism, which takes full consideration of ESD protection operation principles. Therefore, this new CAD tool is different from existing simple ESD spacing and bus resistance checking approaches, and can achieve whole-chip ESD protection verification and prediction. The CAD tool consists of three modules: an ESD device extraction module , an ESD design inspection module and an ESD zapping test module . The ESD extraction module can accurately extract arbitrary ESD protection structures at full chip level. Decomposed-based subgraph isomorphism algorithm is used for ESD device extraction to improve time efficiency. The ESD design inspection module serves to remove non-critical ESD devices extracted based upon a novel smart parametric checking mechanism. The ESD zapping test module is developed to perform complex ESD protection zapping test simulation using Dijkstra's algorithm to resolve the problem of finding the critical ESD discharging path at chip level. The new ESD CAD tool was verified at full chip level using ESD protection designs implemented in 0.35µm BiCMOS technology.

ESD device models were reported for traditional diode and MOSFET type ESD structures. However, due to complex ESD behaviors, particularly the electro-thermal-process-device-circuit-layout coupling effects, the existing ESD models have limited accuracy in describing complex ESD physics and coupling effects, such as thermal boundary condition and snapback I-V behavior.

This thesis presents a new scalable ESD behavioral modeling technique, which uses Verilog-A to develop accurate ESD behavior models for various ESD protection structures, such as novel nano crossbar ESD protection structures, novel 3D field-programmable ESD protection structures using SONOS and NCD ESD devices, silicon controlled rectifier (SCR) based ESD protection structures, HV diode and SCR ESD protection structures, 28nm CMOS gated diode and DTSCR ESD protection structures. The new scalable ESD behavior modeling technique was fully verified by SPICE circuit simulation and transmission line pulse (TLP) ESD testing, which will enable whole-chip ESD circuit design optimization and verification.

Flip chip technique using ball grid ball (BGA) pad-ring arrays is a popular technology for small footprint chips used in size-sensitive electronics. However, ESD protection design for ICs using large BGA pad-ring array is an emerging challenge since where to place an ESD structure becomes a real layout design problem.

This thesis reports design of a BGA pad-ring array with different ESD metal routing for a visible light communication (VLC) transceiver implemented in 180nm BCD technology at whole-chip level. The ESD structures and their ESD-critical parameters, and the ESD metal bus resistance were extracted by our ESD Extractor CAD tool. The new ESD behavior modeling technique was used to model the ESD structures. The extraction and modeling was validated by SPICE simulation and TLP testing for different ESD metal routing.