UC San Diego

The thesis presents advanced millimeter-wave and THz receivers, imaging arrays, switches and detectors in CMOS and SiGe BiCMOS technologies. First, an in-depth analysis of a SiGe BiCMOS on-off keying (OOK) receiver composed of a low noise SiGe amplifier and an OOK detector is presented. The analysis indicates that the bias circuit and bias current have a substantial impact on the receiver and should be optimized for best performance. Also, the LO leakage from the transmitter can have a detrimental impact on the receiver sensitivity and should be minimized for best performance. The receiver consumes 11 mW, has a noise equivalent power (NEP) of 5-10 fW/rtHz¹/² at 55 GHz, and an instantaneous dynamic range of 27-30 dB. The OOK receiver achieves 6 Gb/s communication with a bit-error rate (BER) < 10⁻¹² at room temperature. Operation is also demonstrated up to 105 C at 3 Gb/s with a BER < 10⁻¹². Next, a 0.32 THz 4 x 4 imaging array based on an advanced SiGe technology (Jazz SBC18H3) is presented. Each pixel is composed of a high efficiency on-chip antenna meeting all metal-density rules, which is coupled to a SiGe detector and a low noise CMOS operational amplifier. The array results in an average NEP of 34 pW/rtHz¹/² for a detector bias current of 50-150 [mu]A, a responsivity of 18 kV/W and a 3-dB bandwidth of 25 GHz. The power consumption is 2.4 mW/pixel. Extensive measurements are presented which show the challenges encountered in obtaining accurate measurements at THz frequencies, and the decisions taken to quote the average NEP values. A high performance 0.3 THz 4 x 4 imaging array in a 45 nm silicon-on-insulator (SOI) CMOS technology is also presented. The single element of the array is composed of a high-efficiency on- chip antenna meeting all metal-density rules, which is coupled to a differential detector and a low noise CMOS IF amplifier. The array results in an NEP of 100 pW/rtHz¹/², a responsivity of 1.8-2.0 kV/W with a 3-dB bandwidth of 20 GHz. The power consumption is 3.6 mW/pixel. These values are competitive with the best CMOS THz imaging arrays to- date. For 60 GHz applications, a 45 nm CMOS SOI LNA/phase shifter and an ultra low-loss single-pole double-throw (SPDT) switch in a 90 nm CMOS process are presented. The 3 -bit phase shifter is designed using a switched-LC approach and results in only 6 dB loss at 65 GHz. The LNA/ phase shifter front-end results in a gain of 6.5 dB, a noise figure of 4.3 dB, and an input P1dB of -13.5 dBm (limited by the amplifier) with a power consumption of 15 mW. This work shows that advanced CMOS processes are essential for low power, medium linearity 60 GHz phased arrays. The SPDT switch is based on quarter-wave transmission lines with shunt inductors at the output matching network. The switch results in a measured insertion loss of 1.5-1.6 dB at 53-60 GHz and < 2.0 dB at 50-70 GHz. The measured isolation is > 25 dB, and the output port-to-port isolation is > 27 dB at 50-70 GHz. The measured P1dB is 13.5 dBm with a corresponding IIP3 of 22.5 dBm at 60 GHz. The return loss is better than -8 dB at 50-70 GHz. The active chip area is 0.5 x 0.55 mm² and can be reduced in future designs by folding the quarter- wave transmission lines. When this work was published, it presented the lowest insertion loss 60 GHz SPDT in any CMOS technology to-date. 140-220 GHz single-pole single- throw (SPST) and single-pole double-throw (SPDT) switches built using 45 nm semiconductor-on-insulator (SOI) CMOS technology are presented. A tuned-shunt topology is used to minimize the insertion loss, and the transistor layout results in very low ground inductance and high isolation. The double-shunt SPST switch results in an insertion loss of 1.0 dB and an isolation of 20 dB, while the SPDT switches result in an insertion loss of 3.0 dB and an isolation of 20-25 dB, all at 180 GHz. The switches are well matched with a return loss at all ports greater than 10 dB at 140-220 GHz. The work shows that advanced CMOS nodes can be used for transmit-receive switches in emerging 140-220 GHz CMOS systems. A G-band (140-220 GHz) detector in a 45 nm silicon-on-insulator (SOI) CMOS technology is presented. The measured detector responsivity is 3 kV/W at 170-180 GHz with a 3-dB bandwidth of 150-210 GHz. The detector results in an NEP of 8-10 pW/rtHz¹/² at a bias current of 50-200 [mu]A for an IF of 10 MHz and is well matched with an input return loss > 10 dB at 167-194 GHz. The responsivity and NEP values are close to the best SiGe detectors, and show that advanced CMOS nodes are suitable for ̃200 GHz imaging arrays