UC San Diego

Implementing an application on a FPGA remains a difficult, non-intuitive task that often requires hardware design expertise in a hardware description language (HDL). High- level synthesis (HLS) raises the design abstraction from HDL to languages such as C/C++/Scala/Java. Despite this, in order to get a good quality of result (QoR), a designer must carefully craft the HLS code. In other words, HLS designers must implement the application using an abstract language in a manner that generates an efficient micro- architecture; we call this process writing restructured code. This reduces the benefits of implementing the application at a higher level of abstraction and limits the impact of HLS by requiring explicit knowledge of the underlying hardware architecture. Developers must know how to write code that reflects low level implementation details of the application at hand as it is interpreted by HLS tools. As a result, FPGA design still largely remains job of either hardware engineers or expert HLS designers. In this work, we aim to take a step towards making HLS tools useful for a broader set of programmers. To do this, we made following contributions : 1) we study methodologies of restructuring software code for HLS tools; 2) we provide examples of designing different kernels in state-of-the art HLS tools; 3) we described a theoretical framework for parameterizable HLS templates for composing restructured HLS code based on design patterns, 4) we present a domain-specific framework that generates efficient FPGA designs using pre-optimized HLS templates and design patterns