Lawrence Berkeley National Laboratory

The ATLAS Semi-Conductor Tracker (SCT) Collaboration is currently in the production phase of fabricating and testing silicon strips modules for the ATLAS detector at the Large Hadron Collider being built at the CERN laboratory in Geneva, Switzerland. A small but relevant percentage of ICs developed a new set of defects after being mounted on hybrids that were not detected in the wafer screening. To minimize IC replacement and outright module failure, analysis methods were developed to study IC problems during the production of SCT modules. These analyses included studying wafer and hybrid data correlations to finely tune the selection of ICs and tests to utilize the ability to adjust front-end parameters of the IC in order to reduce the rejection and replacement rate of fabricated components. This paper will discuss a few examples of the problems encountered during the production of SCT hybrids and modules in the area of ICs performance, and will demonstrate the value of the flexibility built into the ABCD3T chip.