UC San Diego

As the core of most digital computing systems, data-path design is essential to determine the whole system performance. I propose two optimization techniques to efficiently minimize power consumption and achieve timing/ area/power tradeoff for specific applications. For prefix adder designs, we develop an integer linear programming method to build optimal prefix adders, which counts gate and wire capacitances in the timing and power models. We also analyze the computation efforts from memory, arithmetic functions and iterations in division operation and propose a hybrid algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms together. These research works optimize data-path designs in different levels from algorithm to logical/physical synthesis. Unlike the previous works, both approaches proposed in the dissertation explore the design space in terms of timing, area and power consumption