UC San Diego

Radio Frequency (RF) transmitters have long been realized by analog circuitry particularly at the front-end that interfaces with the antenna. Migrating wireless transmitter functions from analog to digital circuitry can bring many benefits such as lower cost, lower power, and higher integration while eliminating some of the drawbacks of analog circuitry such as sensitivity to temperature and processing variation. The objective of this dissertation is to investigate and analyze techniques used to implement wireless transmitters with digital circuitry. Several different transmitter designs addressing different wireless standards are presented, which serve to show the advantages of the digital approach, highlight major obstacles to its success with emphasis on the issues unique to digital transmitters, and introduce novel analysis and simulation techniques leading to new designs addressing the obstacles identified. The dissertation begins by summarizing barriers to digital transmitter implementation, and introducing new metrics to facilitate comparative evaluation. In-band power ratio is discussed, a novel metric useful for the prediction of relative efficiency of switching amplifiers driven with different quantization algorithms. The transmitter system examples begin with a low-power standard with relatively low signal accuracy requirement (ZigBee) where a novel quantization algorithm driving a CMOS amplifier highlights the digital transmitter benefits of simplicity, high integration, and low total transmitter power. The dissertation then discusses more complex, higher-power systems (CDMA and WCDMA) to highlight the major obstacles to a cellular- handset-class digital transmitter. Novel optimizations of a delta-sigma modulator's digital implementation and noise transfer function design allow the modulator to operate quietly in the receive band, while retaining realistic clock frequencies and word lengths. Through laboratory measurements, analysis, and fixed-time-step simulations developed in this work, a set of nonlinearities is discovered that is inherent to types of switching amplifiers driven by aperiodic broadband signals. The cause of these nonlinearities is presented, and validated by an amplifier redesign reducing these nonlinearities by more than an order of magnitude. A variation on a well- known digital encoding algorithm, band-pass pulse width modulation, is shown to achieve amplifier efficiencies better than delta-sigma, without exciting broadband noise from amplifier nonlinearities. Novel digital-to-time circuit topologies and frequency domain simulations are presented to attain the high accuracy time resolution needed to achieve pulse width modulation at high frequencies. Laboratory measurements are provided showing the efficiency and noise advantages of this design. digital polar amplification system is presented highlighting novel digital drive algorithms. A general study on broadband noise generated by polar amplifier systems is undertaken with simulation and analysis. Unique time-domain properties of polar broadband noise, due to common impairments such as time misalignment, are presented and analyzed. A pre-distortion technique is presented that can reduce the broadband noise in polar amplifiers though the addition of simple DSP operations. Lastly, a novel all-digital frequency synthesis algorithm is presented along with hardware measurements