UC Santa Cruz

Due to increasing complexity of microprocessor design and a lot of stress on high performance, power consumption and associated heat have reached critical levels. Therefore, the simulation methodology today is adding a new dimension: power optimization. Modern computer architects need to do a comprehensive analysis of power/performance tradeoffs to do a fair design evaluation. Array-based memory structures account for the largest share of power consumption in modern processors. Also, as these components have regular structure, it is easier to model them and quantify their power consumption. As a result, power-reduction approaches primarily focus on memory structures. For array-based components, such as SRAM, cache, CAM, the design search space is very wide. There are large numbers of parameters that need to be optimized given certain main parameters such as size, number of ports, associativity, bus width, etc. The simulation platform must iterate through these parameter values to find the optimal configuration for a given design constraint. The problem is that iterating through these many parameters is extremely slow (may require days) and resource-intensive.

There are energy models such as CACTI, Wattch, and McPAT that can be integrated with architectural simulators to estimate power consumption. However, the issue of fast and comprehensive power consumption analysis has not been addressed well. In our thesis, we focus on improving the time taken by ESESC (\textbf{E}nhanced-\textbf{S}uper\textbf{ESC}alar simulator) to estimate power consumption for SRAM and cache-based structures. The new equation-based power model that we have integrated in ESESC was developed by doing a full design space exploration using CACTI. Using this new power model, called {\em LibPeq}, we get an average speed gain of 16.8\% for large simulation runs and an impressive 99.98\% improvement in initialization time. The new power model can also be integrated with other simulators and energy models that rely on CACTI for power estimation of array-based structures. ESESC, along with this new power model, can be a very strong tool for modern computer architects and researchers looking for power-efficient designs.