UC Riverside

Flash memory is the dominant nonvolatile memory technology that has been experiencing fastest market growth driven by the booming of portable electronic devices. Since its invention in 1980s, it has been through aggressive scaling. Leading semiconductor memory manufacturers such as Samsung, Intel/Micron and SanDisk/Toshiba have unveiled their 19/20nm NAND flash technology in production. However, how long the fast scaling pace of flash can be maintained remains a question mark since this device using continuous polycrystalline Si floating gate faces increasing challenge brought by poor immunity to charge leakage and process difficulty due to large vertical gate stack dimension. To enable the further scaling of flash technology, change needs to be made at the cell level. Devices using discrete charge storage units have been recognized as potential alternatives to conventional flash cells, including charge trapping type device and nanocrystal floating gate device.

Nanocrystal floating gate memory is considered a promising future nonvolatile memory candidate because of its immunity to weak-point leakage in tunnel oxide and thus its superior scalability in terms of tunnel oxide thickness and power consumption. However, no scaling is easy. Problem of nano-dot density fluctuation has arisen for this type of device as scaling process proceeds. The increasing sensitivity of chip-level device performance to dot distribution in scaled cells requires that nanocrystal deposition, which is the key step for device fabrication, should be fully understood, and that this device should start evolving to incorporate material and structure innovations. This work is devoted to propelling the scaling process of nanocrystal memory through nanocrystal deposition behavior investigation and device structure engineering. In chapter 2, Si nanocrystal growth on patterned oxide substrate by chemical vapor deposition is studied both experimentally and theoretically and directed self-assembly behavior of Si nanocrystals is identified as due to the effect of substrate morphology. This deepens our understanding on nanocrystal nucleation and growth and provides a general guidance to deposition process for memory applications. Chapter 3 includes the work on a gate stack-engineered nanocrystal MOS capacitor memory device. An Al2O3-SiO2 double-barrier structure is utilized for dielectric layers and process-induced oxide degradation issue is well solved, resulting in improved memory performance. Chapter 4 and chapter 5 focus on the demonstration of non-planarity concept for nanocrystal memory device. Non-planar nanocrystal memories with multiple and single triangular-shaped Si nanowire channel are introduced. This new concept of nanocrystal memory device is aimed at alleviating dot density variation issue at the scaled technology nodes and helps extend the scaling limit of planar device.

Based on all the theoretical and experimental work in this dissertation, it is concluded that nanocrystal memory scaling lies in good understanding and control of the key process as well as continued cell architecture engineering. This work serves as a step toward the scaling limit of nanocrystal floating gate device for next generation nonvolatile memory development.