Novel High Efficieny CMOS On-Chip Antenna Structures at Millimeter Waves

—In this work, four designs of (Bi)CMOS on-chip antenna (OCA) at 90GHz and 140GHz are shown and compared, aiming at the difficult task of broadside radiation (off the top chip metal surface). A bowtie-shaped slot antenna is fabricated and expected to offer a gain of –1.5dB at 90GHz and 30GHz impedance bandwidth. Another design of slot antenna backed by a cavity, which is fully isolated from the circuits, gives a gain of – 2 dB at 140GHz and 5 GHz bandwidth. Additionally, a design of a slot antenna based on an integrated waveguide in (Bi)CMOS showing –1 dB gain is proposed. At last, a proposed E-shaped patch antenna, which only occupies 0.7 mm× 0.7 mm area, shows –2 dB gain with 10 GHz bandwidth.


INTRODUCTION
Thanks to the fast advancement in semiconductor technology, research efforts in radio frequency ICs have started to focus on the millimeter wave (mmWave) spectrum. Meanwhile antennas, usually one of the largest components in a wireless system, have shown the potential to be integrated alongside the mmWave front-end on a single die. On-chip antennas (OCA) could shrink the size of mmWave wireless systems. To integrate with next generation mmWave singlechip radio [1][2], OCAs have the clear advantage over antennas on printed circuit boards (PCBs) in terms of reduction of feed loss due to the absence of long interconnection. For a typical antenna on a PCB, the feed line is so long that the signal of the chip output has to pass through the wirebond/bump, the interconnection layers in chip package and the feed line on board.
However, it is difficult to achieve high efficiency for (Bi)CMOS OCA because of the low resistivity substrate, and for the extremely thin thickness provided for antenna (between M1 and M6, shown in Fig. 1) and area size restriction. Several CMOS OCAs have been studied whose radiation efficiency is always very poor [1,3]. Others like in [4] propose to increase the gain by covering the whole chip with a lens which needs extra bulky space out of the chip. Meanwhile, the micromachining technique and proton implantation process have been proposed to improve the radiation efficiency by reducing the substrate losses [5][6], but the shielding problem from other circuitry would still remain. including bowtie antenna (from [7]).
One of the major concerns in the integration of OCA is the electromagnetic interference (EMI) resulting from mutual coupling between the antenna and the high frequency front end or other CMOS circuits, that could be significant due to substrate coupling, which could also degrade the proper operating of the integrated antenna. In practice, it is prerequisite to utilize some techniques to reduce the EMI. It should be mentioned that the OCA is not simply a matter of straightforward copy of integrated antennas developed by the process of III-V semiconductor, like GaAs. For instance, through wafer via can be easily realized through the substrate and used as a shield between antenna and circuit in standard GaAs, but not in a standard mainstream silicon process.
In this paper, four different designs of high efficiency antennas, which are all fully on-chip, are demonstrated considering realistic material parameters. The frequency domain HFSS and the time domain solver CST are used for the simulations. Fig. 1(a) illustrates the side (lateral) view of chip environment used in this paper. The silicon substrate has the thickness of 275 μm with the dielectric constant of 11.9 and resistivity of 12.5 •cm.
II. BOWTIE-SHAPED SLOT ANTENNA Fig. 1 (b) shows part of the chip photo of a 90GHz fully integrated passive imaging chip including a bowtie-shaped slot antenna connected to an LNA via a CPW line (in collaborator with L. Gilreath and P. Heydari, UC Irvine.) The antenna is placed at M6 and has an area of 1.4mm × 0.9mm while the whole chip (not shown here) has an area of 1.6mm × 5mm. It is assumed that there is a ground plane below the chip, which could be realized by a package interconnection layer or by a PCB. According to the antenna pattern in the E and H planes in Fig. 2(b), the peak gain at 90 GHz occurs at the broadside direction ( = 0°) and it is around -1.5dB. The 3dB realized gain bandwidth is from 72 GHz to 120 GHz as shown in Fig. 3. However, due to the proximity between the antenna and the circuit, the antenna performance could be greatly affected by interference with the circuit. Since the wave could travel through the substrate, it was observed that the radiation pattern and peak radiation direction are affected by the presence of circuit parts (modeled as a metal plate), when included in the antenna simulation.

III. CAVITY-BACKED SLOT ANTENNA
The top and side view of a cavity-backed slot antenna are shown in Fig. 4. The cavity is placed under the slot antenna between the bottom metal layer M1 and the top one M6 to enhance the antenna radiation and provide a good isolation between antenna and rest of the chip. The side wall of the cavity, shown in Fig. 4(b), is implemented by connecting the metal layers from M1 to M6 using multiple vias in between. The cavity is designed to resonate at its TE 110 mode close to 140 GHz. The slot location and size are optimized to achieve high gain around 140GHz. The antenna is fed by a 50 microstrip line. The total antenna area is 1.2mm × 0.6mm. The width and length of the cavity, the slot width and length, and the slot offset to the center of the cavity are respectively a = 0.6 mm, b = 1.2 mm, L width = 20 μm, L slot = 1 mm, and L offset = 10 μm.
The gain patterns in the E and H planes are shown in Fig.  5(a). The peak gain is around -1.4dB. The cavity under the antenna is used to provide good shielding from the circuitry but also limits the operational bandwidth. It can be observed in Fig.  5(b) that the impedance bandwidth is around 5GHz, from 136GHz to 141 GHz. Fig. 5(c) shows the simulated gain versus frequency of the optimized antenna. The peak appears around 141 GHz and the 3dB gain bandwidth is from 136 GHz to 156 GHz.

IV. EXTREMELY FLAT WAVEGUIDE SLOT ANTENNA
Another potential prototype of slot antenna design using an extremely flat waveguide is proposed, with characteristics like ease of fabrication, low cost, weak interference to the nearby circuit components and also completely isolated with the lossy silicon substrate. The flat waveguide structure is created within a dielectric layer by adding a top metal over the ground plane and caging the structure with rows of plated vias on either side as was done in [8] at mmWave.
Similar to the cavity-backed slot as Fig. 4(b), the waveguide is realized by M1, M6 and multiple vias in between. As illustrated in Fig. 6(a), it looks like a very flat, short ended and dielectric-filled rectangular waveguide, with highly reduced height compared to the "normal" 2:1 width-height ratio. The waveguide is working with its dominant TE 10 mode. Since the cutoff frequency of the dominant mode in a rectangular waveguide is independent of the height, the reduced height does not affect the working frequencies of the waveguide but only reduces the impedance of the wave, which strongly affects losses. The open-end of waveguide is matched to a 50 microstrip line with a tapered transition structure.
As shown in Fig. 6, -1 dB broadside gain at 140 GHz is achieved by using a single integrated waveguide slot antenna in the longitudinal direction. However, because of the extremely flatness (height) of waveguide, the bandwidth of this type of antenna is comparably small (around 3 GHz). The total area of antenna is 0.6mm × 2mm.

V. E-SHAPE PATCH ANTENNA
The E-shaped patch antenna shows wider bandwidth compared with traditional rectangular patch antenna [9]. Two additional slots are introduced at one side of the patch to pull in another resonant frequency in addition to the resonant frequency of rectangular patch. When the two resonant frequencies get close, wider bandwidth could be achieved.
In the design shown in Fig. 7(a), the slot length L T , sloth width L W and the slot location L offset are optimized in the way such that the two resonant frequencies get close to each other around 140 GHz. Fig. 7(a) shows the top metal layer of the proposed E-shaped patch antenna, which is on M6 of CMOS structure while M1 is set as ground plane as indicated in Fig.  7(b). Note that the presence of ground plane of the patch at M1 could effectively reduce the electromagnetic interference between antenna and RF front-end by shielding the wave travelling through the silicon substrate. Vias between M1 and M6 could also be introduced close to the patch edges without altering significantly the operation. The antenna is fed by a 50 microstrip line. The width and length of the patch, the slot width and length, and the slot's offset to side of patch are respectively a = 0.51 mm, b = 0.655 mm, L width = 37 μm, L slot = 165 μm, and L offset = 110 μm. The total antenna area, when including the ground plane, is 0.7 mm × 0.7 mm.
The accepted gain pattern in the E and H planes of the Eshape patch antenna are shown in Fig. 7(c) and the simulation results are verified by two simulators, CST and HFSS. The results from two solvers are in good agreement. Also, from the plot of input impedance shown in Fig. 7(d), one can observe the two resonances, at 141 GHz and at 146 GHz. The -10 dB reflection impedance bandwidth is around 10 GHz, from 138 GHz to 148 GHz.

VI. CONCLUSION
Four types of novel on-chip antenna structures based on (Bi)CMOS process are proposed in this study. Numerical simulation by HFSS and CST are utilized to examine the antennas' performance. It should be noted that the cavitybacked slot antenna, flat waveguide slot antenna, and the Eshaped patch antenna all use M1 as ground plane. Therefore, all these designs could reduce the EMI effectively. The E-shape patch antenna shows a greater degree of miniaturization and larger bandwidth.