A Multi-Phase Cascaded Series-Parallel (CaSP) Hybrid Converter for Direct 48

—The rapid growth in data-center electricity consumption has created an imperative need for more energy-efﬁcient solutions to data center power delivery. This work proposes a multi-phase hybrid switched-capacitor (SC) converter for direct 48 V to point-of-load (PoL) conversion with high performance. The proposed topology can be viewed as a 6-to-1 cascaded series-parallel (CaSP) converter merged with a three-phase interleaved buck converter with automatic current balancing. Due to multi-phase operation, the CaSP stage is able to achieve a higher conversion ratio compared to two-phase SC converters with the same number of components as well as lower turn-on voltage for switching devices. Moreover, the proposed CaSP-PoL topology beneﬁts from the frequency multiplication effect similar to that in ﬂying capacitor multilevel converters, which allows for lower frequency operation of higher voltage rated switches and doubled frequency operation of buck inductors, contributing to a further reduction in switching loss and inductor size. A 48 V-to-PoL hardware prototype was built in vertical assembly structure for compact packaging and tested up to 90 A output current, achieving 94.1% peak efﬁciency (93.2% including gate drive loss) and 702 W/in 3 power density (by box volume) at 2.0 V output voltage.


I. INTRODUCTION
Data-center electricity consumption accounted for about 1% of global electricity demand in 2018 and is forecasted to increase to 8% of projected global demand by 2030 [1], [2].This rapid growth of computationally intensive information industry has made it imperative to develop more energyefficient solutions for data center power delivery.Compared to the conventional 12 V bus, the 48 V bus has been demonstrated to be capable of achieving higher overall efficiency due to lower rack distribution loss [3] and therefore has received increased attention in modern data centers.This means that the 48 V bus then needs to be stepped down to the Point-of-Load (PoL) which requires extreme low voltage (e.g.1.0-2.0V) and high current (e.g. 100 A and higher).
To achieve such a high step-down conversion ratio, the most straightforward approach is the two-stage architecture [4]- [6] in which the 48 V bus is first stepped down to an intermediate bus (e.g. 12 V) with a bus converter and then regulated down to the load with a PoL converter.Compared to the two-stage approach, direct 48 V-to-PoL conversion has been demonstrated in recent works [7]- [13] to be promising for higher overall system efficiency and power density.These works can be classified into two categories: transformerbased solutions [7], [8] and hybrid switched-capacitor (SC) solutions [9]- [13].The former comprises an optimized LLC converter with high step-down ratio and customized magnetics merged with a buck converter, whereas the latter comprises a fixed-ratio SC converter merged with a buck converter.Compared to transformer-based solutions, hybrid SC converters demonstrate more efficient utilization of switches [14] and can leverage the superior energy density of capacitors compared to inductors and transformers [15].By merging the SC and buck stages, the total number of components can be reduced in comparison to the two-stage cascading structure.More importantly, the addition of the buck inductors allows for softcharging operations of the SC stage, enabling highly efficient conversion [16], [17].
This paper proposes a multi-phase hybrid SC converter that can achieve direct 48 V-to-PoL conversion with high efficiency and high power density.The proposed topology comprises a 6-to-1 cascaded series-parallel (CaSP) stage and a three-phase interleaved buck stage with automatic current balancing.Due to multi-phase operation, the CaSP stage is able to achieve a higher conversion ratio compared to twophase SC converters with the same number of capacitors and switches and enable lower turn-on voltage for the switching devices.The proposed CaSP-PoL topology also benefits from the frequency multiplication effect similar to that in flying capacitor multilevel (FCML) converters, which allows for lower frequency operation of higher voltage rated switches and doubled frequency operation of the buck inductors, further contributing to a reduction in switching loss and inductor size.A 48 V-to-PoL hardware prototype was built in vertical assembly structure to achieve compact packaging and tested up to 90 A output current.At 48-to-2.0 V conversion, the prototype achieved 94.1% peak efficiency (93.2% including gate drive loss) and 702 W/in 3 power density (by box volume).

II. PROPOSED TOPOLOGY AND OPERATING PRINCIPLES
Fig. 1 shows the schematic of the proposed CaSP-PoL converter, with the voltage rating and operating frequency of the main active and passive components listed in Table I.Fig. 2 illustrates the key current waveforms and control signals, with the equivalent circuit model for each phase shown on the right.The proposed topology can be viewed as a 6to-1 CaSP converter merged with a three-phase interleaved buck converter.The CaSP structure, on the one hand, can be regarded as a 2-to-1 front-end stage followed by a 3-to-1 series-parallel stage.On the other hand, it can also be derived from the classic 4-to-1 series-parallel topology, by moving the source terminals of Q 2 , Q 5 and Q 6 from the left-side of L 3 to the positive-side of C 2 and the left-sides of L 1 and L 2 , respectively, and removing the switch between the negativeside of C 3 and the left-side of L 3 .
As illustrated in Fig. 2, each switching cycle of the proposed converter is divided into multiple phases.The charge and discharge of C 2 and C 3 each takes two phases.C 1 is charged in phase 1 and discharged in phase 4, whereas C 2 and C 3 are charged in phases 1 and 4. C 2 is discharged in phases 2 and 5, and C 3 is discharged in phases 3 and 6.Due to the high conversion ratio of the CaSP stage, the conversion burden on the buck stage is reduced.Another advantage of multi-phase operation is lower turn-on voltage of switching devices.As can be seen in Fig. 2, although Q 7 's peak blocking voltage is Vin  3 , its drain-to-source voltage V ds,Q7 naturally drops to a lower level before it turns on, contributing to reduced switching loss.
In the proposed CaSP-PoL topology, the CaSP stage and the three-phase buck stage are merged together without additional switches or flying capacitors.This helps not only minimize the number of components but also reduce the conduction loss compared to a two-stage approach, contributing to both higher power density and higher efficiency.The operation of the CaSP and buck stages is merged seamlessly to ensure interleaved inductor currents.Each inductor is energized twice in a switching cycle in two different phases by the source or flying capacitors and de-energized twice in the freewheeling phase 7.
The three-phase buck stage has an automatic current balancing capability that is similar to that of the series capacitor buck converter [18], [19].There is a negative feedback mechanism that keeps the average currents through L 1 and L 2 the same as that through L 3 , so that the three inductor currents are naturally balanced.For example, if the average current through L 1 is higher than that through L 3 (i.e.i L1 > i L3 ), then the net charge flowing into C 2 in phases 1, 2, 4 and 5 will be negative, meaning C 2 will be discharged.Therefore, the voltage across L 1 in phases 2 and 5 in which L 1 is energized will decrease while the voltage across L 3 in phases 1 and 4 will increase, so that i L1 will decrease and i L3 will increase correspondingly until i L1 = i L3 .A similar analysis can be applied to i L2 and i L3 .If i L2 < i L3 , then the net charge flowing into C 3 in phases 1, 2, 3 and 6 will be positive, meaning C 3 will be charged.Therefore, the voltage across L 2 in phases 3 and 6 in which L 2 is energized will increase while the voltage across L 3 in phases 1 and 4 will decrease, so that i L2 will increase and i L3 will decrease until i L2 = i L3 .In summary, such a negative feedback mechanism naturally ensures i L1 = i L3 and i L2 = i L3 so that the threephase interleaved inductor currents can be naturally balanced.
In addition, the abovementioned automatic current balancing capability can also be explained with a more quantitative analysis.Due to the triangular shape of the inductor currents, the average inductor current in the rising and falling stages will be the same as the average current over one switching cycle in the periodic steady state (PSS).Therefore, in PSS, the average currents through the flying capacitors can be given as In PSS, the average currents through the flying capacitors should be zero, i.e.Moreover, the proposed CaSP-PoL converter benefits from the frequency multiplication effect similar to that in FCML converters.If C 1 and Q 1 -Q 4 operate at a frequency f 0 , then the other main components operate at a frequency 2f 0 .As listed in Table I, the switches with higher voltage ratings (Q 1 -Q 4 ) operate at lower switching frequency than those with lower voltage ratings, which is favorable to switching loss reduction.Since the operating frequency of the inductors is doubled due to multi-phase operation, lower inductance can be chosen while maintaining the same inductor current ripple.Also, due to the reduced switch voltage stress in the CaSP stage, low-voltage MOSFETs with lower R ds(on) and lower switching loss can be used.In addition, Q 9 -Q 11 operate with zero-voltage switching (ZVS) turn-ON.
The conversion ratio of the proposed converter can be de- rived based on the volt-second balance of the buck inductors: where D is the duty ratio of phases 1 − 6 with respect to T 6 , as illustrated in Fig. 2. Therefore, the output voltage can be regulated by adjusting the duty cycle.

III. HARDWARE IMPLEMENTATION AND EXPERIMENTAL RESULTS
Figures 3 and 4 show the annotated photograph and 3D assembly drawing of the converter prototype, with the key parameters and component list tabulated in Tables II and III, respectively.
As illustrated in Fig. 4, the prototype consists of two vertically stacked PCBs connected via nodes v sw1 , v sw2 , v sw3 and v out (labeled in Fig. 1) with thick copper sheets (0.5 mm thick for v sw1 , v sw2 and v sw3 , and 1.0 mm thick for v out ). PCB 1 contains the switches, flying capacitors and gate drive circuitry while the inductors are placed on PCB 2. This vertical structure can not only ease the layout design since it offers an addition dimension for component placement but also facilitate full utilization of the box volume of the converter.Commercial inductors with the desired parameters and the small footprint required in this design are typically high-profile with a height of more than 7 mm and are significantly taller than the other components (e.g.MOSFETs and capacitors) that are lower than 2 mm.If the inductors are placed on the same board with the other components, it would be difficult to achieve the smallest possible box volume since the large space above the low-profile components could not be utilized.Instead, by stacking the high-profile inductors and the other low-profile components in the way illustrated in Fig. 4, all main components are tightly packaged within a In this prototype, efficiency is slightly traded for higher power density.Therefore, the selection of inductor is first based on the suitable footprint size that can be packaged with the other components in a rectangular box.Additionally, to achieve high efficiency, inductors with high inductance and low DCR should be selected.Finally, the TDK VLBU805080T-R18L with 5 × 8 mm footprint, 180 nH inductance and 0.2 mΩ DCR was selected.For each inductor (L 1 -L 3 in Fig. 1), two TDK VLBU805080T-R18Ls are connected in series.As for the selection of flying capacitors, the capacitance design in this regulated converter is largely relaxed compared to the resonant converters [20] in which the L and C values have to be precisely tuned.Relatively small flying capacitors can be employed as long as they can ensure sufficiently small capacitor voltage ripples that will not cause overvoltage  breakdown of switching devices and imbalanced inductor currents.Choosing larger flying capacitors can help reduce total capacitor ESR and hysteresis loss [21], [22] and ensure well-balanced inductor currents.
As listed in Table I, due to the reduced switch voltage stress in the CaSP stage, low-voltage MOSFETs with lower R ds(on) and lower switching loss can be used (40 V for Q 1 -Q 5 and 25 V for Q 6 -Q 11 ).An additional switch is added in parallel to Q 11 to reduce the conduction loss since it carries two-times higher peak current than Q 9 and Q 10 .The floating switches are driven by high-side gate drivers with internal level-shifters that are powered by a cascaded bootstrap circuit [23].The gate drive voltage is 7.0 V in this prototype.The output voltage is regulated with a hysteretic control on the duty cycle D in which D will be increased by a step ΔD if the measured output voltage is lower than the reference value and will be reduced by ΔD if the measured output voltage is higher than the reference value.More advanced control techniques can be employed for desired transient response and control bandwidth, but are not the focus of this work.PCB 1 has 6 layers and is fabricated with 3 oz copper on the outer layers and 2 oz in the inner layers.PCB 2 has 2 layers and is fabricated with 3 oz copper.Thicker outer copper can be used to help further reduce the PCB trace loss.
Figs. 5(a) and (b) show the measured waveforms of the inductor currents and switch node voltages, respectively.As can be seen in Fig. 5(a), the three-phase interleaved inductor currents are naturally well-balanced which verifies the automatic current balancing capability explained in Section II.tested to 1.2 V due to the limited capability of the electronic load Rigol DL3031 whose minimum operating voltage is 1.3 V at 60 A. The prototype was tested up to 90 A output current and achieved a current density of 351 A/in 3 .At 48-to-2.0 V conversion and f 0 = 160 kHz switching frequency (320 kHz seem by the inductors), the prototype achieved 94.1% peak efficiency (93.2% including gate drive loss) and 90.2% full load (89.9% including gate drive loss), and 702 W/in 3 power density (by box volume).Fig. 8 shows the thermal image of the prototype at equilibrium with fan cooling only at V out = 1.2 V, I out = 90 A, and 27.8 • C ambient temperature.As shown in Fig. 8, the maximum temperature on the board is 91.8 • C. Note that better thermal performance can be achieved by adding heat sinks on the MOSFETs without increasing the box volume since there is still room above the MOSFETs as illustrated in Fig. 4(a).
Table V compares this work with several best existing hybrid SC works with similar voltage conversion ratios.It can be seen that the proposed CaSP-PoL converter achieves a very high power density, while maintaining excellent peak and full-load efficiency.Note that some power density numbers in Table V are calculated by box volume, while others are by power component volume which can be much smaller than the real box volume of the converter.For reference, the power density by power component volume of our design is also provided in Table V.As explained above, the vertical assembly structure is adopted in this prototype to help package all main components in a rectangular box, which necessitates the use of power connectors to join the two PCBs.Since the power connectors at switch nodes v sw1 , v sw2 and v sw3 conduct inductor currents i L1 , i L2 and i L3 that ripple at 320 kHz, the addition of the power connectors incurs not only additional DC conduction loss but also AC conduction loss that cannot be easily reduced by increasing the thickness of the copper sheets due to the skin effect.Therefore, this prototype is designed to trade efficiency for relatively better power density.This can be seen in Table V as this prototype achieved 1.8 times higher power density at the cost of around 1% lower efficiency compared to the MLB-PoL converter proposed in [11].For further optimization, low-profile customized inductors and board cutouts for recessing inductors can be used so that the inductors in this converter could be placed on the same board with the rest of the components without increasing the overall height of the converter, which could remove the need for power connectors and help achieve higher efficiency.

IV. CONCLUSION
This paper presents a multi-phase hybrid SC converter for direct 48 V-to-PoL conversion with high efficiency and high power density.The proposed topology comprises a 6-to-1 cascaded series-parallel (CaSP) stage and a three-phase interleaved buck stage with automatic current balancing.It benefits from the multi-phase operation and frequency multiplication effect which help decrease the number of components, reduce the switching loss, and shrink the inductor size.A 48 V to 2.0-1.2V hardware prototype was built and assembled vertically to facilitate compact packaging and achieve high power density.The prototype was tested up to 90 A output current, achieving 94.1% peak efficiency (93.2% including gate drive loss) and 702 W/in 3 power density (by box volume) at 2.0 V output voltage.

Fig. 1 :
Fig. 1: Schematic of the proposed CaSP-PoL converter with device ratings labeled in blue and control signals labeled in red.

Fig. 2 :
Fig. 2: Key current waveforms and control signals of the proposed hybrid SC converter.The equivalent circuit model for each phase is shown on the right.

Fig. 7 :
Fig. 7: Measured efficiency of the prototype at various output voltages.(a) Power stage efficiency.(b) System efficiency (including gate drive loss).

TABLE I :
Voltage rating and operating frequency of the main components

TABLE II :
Key parameters of the prototype * The converter prototype is able to operate at 1.0 V and lower output voltages but was only tested to 1.2 V due to the limited capability of the electronic load.+The power components included in the volume calculation are switching devices, capacitors and inductors.0.71 × 0.63 × 0.57 inch box with most space inside the box effectively utilized.

TABLE III :
Component list of the prototype * The capacitance listed in this table is the nominal value before DC derating.

TABLE IV :
Measured efficiency and power density of the prototype at various output voltages The volumetric power density listed here is calculated based on the prototype box volume in Table II.The areal power density listed here is calculated based on the prototype box area 0.71 × 0.63 inch (18.1 × 16.0 mm) shown in Fig. 3. ZVS turn-ON of Q 11 .v ctr : PWM control signal, v gs : gate-to-source voltage, v ds : drain-to-source voltage. *