Modeling and Analysis of Switched-Capacitor Converters With Finite Terminal Capacitances

In pre-existing analytical models of switched-capacitor (SC) converters, the input and output capacitances (<inline-formula><tex-math notation="LaTeX">$C_{\text{in}}$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">$C_{\text{out}}$</tex-math></inline-formula>) have long been assumed to be infinitely large so that the input and output can be modeled as ideal voltage sources. However, in practice, the terminal capacitances can be insufficient to ensure ideal input and output behaviors due to space and cost constraints. This article reveals that finite terminal capacitances can have considerable effects on the output impedance (<inline-formula><tex-math notation="LaTeX">$R_{\text{out}}$</tex-math></inline-formula>) and overall efficiency of SC converters. A general modeling and analysis methodology is proposed for SC converters to characterize the effects of finite terminal capacitances quantitatively. A 2-to-1 SC converter prototype is specially designed to verify the proposed general output impedance model. The relative error between the modeling results and the experimental measurements is less than 8%, which demonstrates the excellent accuracy of the proposed model. It is revealed that the insufficiency in <inline-formula><tex-math notation="LaTeX">$C_{\text{in}}$</tex-math></inline-formula> can lead to a considerably higher <inline-formula><tex-math notation="LaTeX">$R_{\text{out}}$</tex-math></inline-formula> and harm the overall efficiency. On the contrary, decreasing <inline-formula><tex-math notation="LaTeX">$C_{\text{out}}$</tex-math></inline-formula> can counter-intuitively help reduce <inline-formula><tex-math notation="LaTeX">$R_{\text{out}}$</tex-math></inline-formula>, which contributes to both higher efficiency and higher power density, although this benefit comes at the cost of a larger output voltage ripple. In addition, <inline-formula><tex-math notation="LaTeX">$C_{\text{out}}$</tex-math></inline-formula> has a stronger effect on <inline-formula><tex-math notation="LaTeX">$R_{\text{out}}$</tex-math></inline-formula> in the slow switching region, while <inline-formula><tex-math notation="LaTeX">$C_{\text{in}}$</tex-math></inline-formula> is more influential in the fast switching region, especially around the knee of the output impedance curve, which is the typical operating point of SC converters. Several design guidelines are provided based on these findings. Further discussions are provided to explain how to apply the proposed general output impedance model to arbitrary SC topologies.


I. INTRODUCTION
C OMPARED with traditional magnetic-based power con- verters, switched-capacitor (SC) converters have been demonstrated to have great potential of achieving higher power density and more effective switch utilization [1], [2].Therefore, The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail: yczhu@berkeley.edu;yezichao@berkeley.edu;pilawa@berkeley.edu).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TPEL.2023.3313562.
Although pre-existing models [18], [19], [20], [21], [22], [23], analyses [24], [25], [26], [27], [28], [29], [30], and control [31], [32] of SC converters assume input and/or output to be ideal voltage sources, as illustrated in Fig. 1(a), practical implementations of SC converters involve input and output capacitors (C in and C out ) to stabilize the terminal voltages, as shown in Fig. 1(b).Theoretically, if C in and C out are much larger than the flying capacitor (C fly ) (i.e., C in , C out 10C fly ) the input and output can be regarded as ideal voltage sources.However, in practical applications, the sizes of C in and C out are usually constrained by space and cost and thus can be insufficient to ensure ideal input and output behaviors.Fig. 2 illustrates the schematic drawing of a 2-to-1 SC converter with finite terminal capacitances, with the simulated output impedance curves with different terminal capacitances presented in Fig. 2(b).As shown in Fig. 2(b), the output impedance curve can significantly deviate from the ideal scenario when the terminal capacitances are insufficient.
Although terminal capacitances can have considerable effects on the output impedance, there is currently no analytical tool that is able to characterize their effects quantitatively.The selection of C in and C out in the design of SC converters is mainly based on engineering experiences and trial and error.However, since the die area is typically limited and valuable in integrated circuits, such as CMOS converters, quantitative optimizations should be performed to find out the best combination of flying capacitances and terminal capacitances to achieve the lowest output impedance within the limited area.This indicates a need for a general analytical tool to characterize the effects of terminal capacitances in SC converters, which can help practicing engineers and researchers achieve the optimum converter size and performance.
This article expands upon our earlier conference publication [33] with more detailed analyses, enriched design guidelines, and further explanations for the applicability of this work to arbitrary SC topologies.In this article, a general modeling and analysis methodology for SC converters is proposed to characterize the effects of finite C in and C out .Section II explains the derivation of the proposed general output impedance model in detail.In Section III, a 2-to-1 SC converter prototype is specially designed for model verification, and the modeling results agree well with experimental measurements with less than 8% relative error.To facilitate analysis, the proposed model is approximated by using Taylor expansion in Section IV-A to obtain a simpler mathematical form.Based on the proposed model, it is revealed in Section IV-B that the insufficiency of C in can lead to a significant increase in output impedance, while smaller C out can counter-intuitively help reduce the output impedance and achieve higher efficiency, although this benefit comes at the cost of a larger output voltage ripple.It is also revealed in Section IV-C that the parasitic source inductance and the deadtime can have a nontrivial impact on the output impedance in the slow and fast switching regions, respectively.Based on the abovementioned findings, Section IV-D provides several design guidelines.Further explanations for the  applicability of the proposed model to arbitrary SC topologies are given in Section V.

A. Circuit Model
In a general circuit state (or phase) k, an SC topology can be viewed as an RC network and represented as the circuit model shown in Fig. 3.It consists of an equivalent resistance R k and an equivalent capacitance C k connected in series.With suitable (topology-dependent) R k and C k parameters, this general expression can capture any arbitrary SC topologies.The method of calculating the model parameters R k and C k for arbitrary SC topologies will be provided in Section V-A.
As illustrated in Fig. 3, two cases should be considered due to the finite input capacitance.The SC converter can be represented as Fig. 3(a) when the input terminal is connected to the source and as Fig. 3(b) when the input terminal is grounded.As conventionally done in topology analysis, the second-order circuit model shown in Fig. 3 can be further simplified as the first-order model illustrated in Fig. 4. First, due to the existence of the parasitic source inductance L p(in) and the high-frequency operation of SC converters (SC converters typically operate above the critical switching frequency to reach the fast switching limit (FSL) [18]), it can be assumed that the input current ripple is sufficiently small so that V in and L p(in) together can be regarded as a constant current source I in .Second, since the output voltage ripple is typically designed to be small compared to the average dc output voltage, the ripple on the output current through the resistive load can also be ignored.In addition, some loads are inherently inductive and behave like current sources.Thus, the load can be modeled as a constant current source I out .

B. Calculation of Output Impedance
By definition, the resistive output impedance R out accounts for all conduction losses and charge sharing losses in an SC converter.Therefore, R out can be calculated with the average conduction loss P loss as Note that P loss is the power loss averaged in one switching cycle and thus can be expressed with the summation of the energy losses over all phases as where f sw is the switching frequency.E k represents the energy loss in phase k and can be calculated as in which i k is the current through R k in phase k and T k(eff) is the effective duration of the phase k.Since there is no forced freewheeling operation in SC converters during the deadtime, the effective duration of phase k is where T k is the duration of phase k and t d is the deadtime.

C. Model Derivation
As indicated by (1)-(3), to calculate the output impedance, we need to find the explicit expression of i k in all phases based on the first-order simplified model shown in Fig. 4 as where I 0 k and I fk are the initial value and forced component of i k in phase k, and τ k represents the time constant of the equivalent circuit.τ k and I fk can be expressed as in which C k(eff) is the effective capacitance and p k is a dimensionless ratio.In the two cases illustrated in Fig. 4, for an m-to-n SC converter, C k(eff) and p k can be given as Case 1 : Substituting ( 2)-( 7) into (1) yields where (9) in which a k is the ratio of the transferred charged in phase k to the total delivered charge in a switching cycle.A detailed derivation of ( 8) is provided in Appendix A. The definition and calculation of a k can be found in [18].
With ideal input and output, C k(eff) and p k become C k(eff) = C k and p k = 0, so that which is the same as has been derived in [22].

III. MODEL VERIFICATION
In this section, a 2-to-1 SC converter prototype is designed to investigate the influence of terminal capacitances on the output impedance quantitatively.The accuracy of the proposed general model is verified by comparing the modeling results with circuit simulations and experimental measurements from 2-to-1 SC converter prototype.

A. Experimental Setup
Figs. 5 and 6 present the schematic drawing and photograph of the 2-to-1 SC converter prototype for model verification, with the main components listed in Table I.The test condition is V in = 24 V and I out = 1 A. The input and output voltages are measured with digital multimeters Keysight 34405 and 34401 A, respectively, and the output current I out is measured by the Eload Rigol DL3031.
For the 2-to-1 SC converter shown in Fig. 6, the topologydependent parameters in the output impedance model are 2 , and , where C fly is the flying capacitance, R on is the ON-state resistance of the GaN HEMT Q 1 -Q 4 , R CS is the value of current sense resistors R CS1 -R CS4 , and ESR C(fly) is the equivalent series resistance (ESR) of C fly .The reason why R CS1 -R CS4 are added in series with the GaN switches will be explained in the following section.

B. Experiment Design Considerations
There are two key considerations to achieve effective model verification: Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.KEMET C2220C474J5GACTU is a class 1 capacitor with C0G dielectric that can maintain high capacitance stability over a wide range of operating temperature and voltage bias and has extremely low ESR and equivalent series inductance (ESL).Therefore, we select it for C fly , C in , and C out , so that the variation in the capacitances can be minimized and ESR C(fly) can be ignored (i.e., ESR C(fly) ≈ 0).

TABLE I COMPONENT LIST OF THE 2-TO-1 SC CONVERTER PROTOTYPE
The ON-state resistance of switching devices can vary significantly due to the changes in operating conditions (e.g., junction temperature, drain-to-source current, gate-to-source voltage, etc.).The ON-state resistance of GaN HEMTs is particularly hard to accurately capture due to the dynamic ON-state resistance phenomenon [34], [35].
To tackle this challenge, we add a high-precision current sense resistor (KOA Speer SLN5TTEDR200D) in series with each GaN switch to dominate the branch resistance.The current sense resistor can maintain high thermal stability (75 PPM/ • C) and has a much higher resistance (R CS = 200 m Ω) than the GaN switch (R on = 16 mΩ @ 25 • C).As a result, the branch resistance can be stabilized by the current sense resistor against the variation in R on .In addition, the cascaded bootstrap circuit with LDOs [36] is selected to drive the GaN switches since it can ensure stable gate drive voltage V drive and minimize the variation in R on resulting from the change in V drive .
2) Minimize the proportion of switching loss: The proposed output impedance model can only capture the conduction losses and charge sharing losses in the SC converter.Therefore, to achieve effective model verification, we need to ensure that the converter operates in the conduction-loss-dominant condition, and the switching loss takes up only a small proportion of the total loss.Meanwhile, the converter needs to operate above 1 MHz to reach FSL.Therefore, we use GaN switches with small output capacitance and low gate charge and set the external gate resistance as 0 Ω to minimize the overlap loss.

C. Experimental Results
Figs. 7 and 8 show the comparison between the output impedances predicted by the proposed model (Model), simulated by PLECS (Sim.), and measured from the converter prototype (Expt.).Figs.7(c) and 8(c) present the relative error of the modeling results with respect to the experimental measurements that is calculated by where R out(Model) and R out(Expt.)are the output impedance predicted by the model and measured from the prototype, respectively.
As can be seen in Figs.7 and 8, the modeling results are in excellent agreement with the circuit simulations and the experimental measurements.The relative error of the modeling results with respect to the experimental measurements is less than 8% for various C in and C out within 100 kHz-2 MHz switching frequency range, covering the slow switching limit (SSL) and FSL.This indicates excellent accuracy of the proposed general output impedance model and its applicability in a wide range of switching frequency.
It should be noted that the relative error grows higher when the switching frequency increases.This is mainly due to the increase in the switching loss resulting from higher switching frequency.In addition, the relative error rises dramatically as the switching frequency decreases when C in is small.This results from the undesired oscillation between L p(in) and C in , which will be further explored in Section IV-C.

IV. EFFECT ANALYSIS OF TERMINAL CAPACITANCES
With the general model derived and verified in Sections II and III, we will use it to explore the effect of finite terminal capacitances on the output impedance of SC converters in this section.

A. Model Approximation by Taylor Expansion
Although the general output impedance model is accurate within a wide range of switching frequency, it can be too complex to provide intuitive engineering insight.The existence of the hyperbolic function coth(x) makes it hard to handle mathematically.Therefore, to facilitate analysis, we approximate (8) with Taylor expansion to obtain a simplified mathematical form.Inspired by the concepts of SSL and FSL [18], we perform model approximation in the slow and fast switching regions separately, and name the obtained models as slow switching model (SSM) and fast switching model (FSM), respectively.
For simplicity, here we perform the approximation to the model of the 2-to-1 SC converter prototype presented in Section III as an example.Note that this approximation technique is applicable to arbitrary SC topologies.To simplify calculation, we set R CS = 0 Ω and assume negligible capacitor ESR and deadtime t d .In the following examples in Sections IV-A and IV-B, C fly = 10 μF, R on = 10 mΩ.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Using Taylor expansion, we can approximate the output impedance model given in (8) for a 2-to-1 SC converter as where in which s is a dimensionless product of the switching frequency f sw and the time constant R on C fly and is defined as the normalized switching frequency.Parameter s c is the critical normalized frequency that marks the boundary between SSM and FSM, and k in and k out are the ratios of C fly to C in and C out , respectively.The detailed derivation of ( 12) is given in Appendix B. Fig. 9 shows the comparison between the precise model given in (8) and the approximated models (SSM and FSM) shown in (12).Table II lists the maximum relative errors of the approximated model with various C in and C out .From Fig. 9, we can see that the maximum relative error always appears at the critical frequency s c .Table II shows that SSM and FSM can approximate the precise model within 8% relative error except for the cases with extremely small C in .
In the slow switching region that ensures complete charge transfer, we have s 1 that yields the SSL in (14).When the switching frequency is sufficiently high so that the current through C fly is almost constant in each phase, s 1 and therefore yields the FSL in the following: When the terminal capacitances are sufficiently large so that the input and output can be regarded as constant voltage sources, k in and k out are approximately zero so that we get R SSL = 1 4C fly f sw and R FSL = 2R on , which is expected and well-known.

B. Effect of Finite Terminal Capacitances
In this section, we first evaluate (12) to analyze the effect of terminal capacitances qualitatively, then perform quantitative analysis with numerical calculations, and finally explore the physical origins for these effects with circuit simulations.
1) Qualitative analysis: In the SSM of (12), when C in becomes smaller, k in increases so that c becomes greater, resulting in higher R SSM .Conversely, with smaller C out , k out increases so that c becomes smaller, contributing to lower R SSM .It is favorable, although counter-intuitive, that decreasing C out can help reduce the output impedance since this will contribute to both higher power density and higher efficiency.But note that this benefit comes at the cost of a larger output voltage ripple.C out should still be sufficiently large to satisfy any ripple constraint.
In the FSM of ( 12), the coefficient d is only dependent on k in while it is independent of k out .This indicates that C out has little effect on R FSM .By inspection, we can predict that reducing C in will lead to higher R FSM .
2) Quantitative analysis: Figs. 10 and 11 show quantitative comparisons of the output impedance of 2-to-1 SC converters with different terminal capacitances.To generalize the analysis, Figs. 10 and 11 are plotted with the normalized switching frequency s in (13) (s = 8f sw R on C fly ), with the output impedance normalized to the FSL impedance as R out /R FSL (R FSL = 2R on ).It can be observed that smaller C in leads to higher output impedance, while the output impedance becomes lower when C out is smaller.
As has been predicted in the qualitative analysis, C out has no influence on the output impedance in the fast switching region.Instead, C in exhibits a greater effect in this region, especially  around the knee of the output impedance curve.Since SC converters typically operate around the knee point, C in should be carefully designed to avoid the undesired increase in the output impedance due to insufficient C in .These findings are consistent with those from the qualitative analysis and the experimental results presented in Figs.7 and 8.
In addition, it can be observed in Fig. 7 that C in = 3C fly is sufficient to approximate an ideal input.However, further reduction in C in can cause a significant increase in the output impedance, which harms efficiency.On the contrary, smaller C out can always help reduce the output impedance.Moreover, in the slow switching region, C out exhibits a stronger influence on the output impedance than C in .For example, Fig. 10(b) shows that reducing C in to 0.25C fly can increase R out by a factor of 1.5, while it is presented in Fig. 11(b) that reducing C out to 0.25C fly can decrease R out by a factor of 0.3.
3) Physical origins: Fig. 12 compares the simulated waveforms of the 2-to-1 SC converter with large and small input capacitances, assuming ideal output.Fig. 12 shows that with smaller C in , the voltage difference seen by C fly (V C(in) − V C(out) − V C(fly) ) becomes much larger.This results in a higher peak value of i C(fly) in the case 1 shown in Fig. 4. Consequently, as listed in Table III, the rms value of i C(fly) becomes higher when C in is smaller, which leads to greater loss and higher output impedance.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 13 presents a similar comparison of output impedance between the 2-to-1 SC converter with large and small output capacitances, assuming ideal input.As listed in Table IV, the rms value of i C(fly) becomes lower with smaller C out .This is because the output voltage (V C(out) ) is able to follow V C(fly) more rapidly when C out is smaller.Consequently, i C(fly) drops faster and thus has a lower rms value, which contributes to less loss and lower output impedance.

TABLE III COMPARISON BETWEEN THE RMS AND PEAK-TO-PEAK VALUES OF
In summary, reducing C in exacerbates the imbalance of capacitor voltages between the two cases of Fig. 4, which increases the rms value of i C(fly) .On the contrary, decreasing C out accelerates the charge sharing processes, thus resulting in a lower rms value of i C(fly) .This accounts for the opposite effects of C in and C out on the output impedance of SC converters.Experimental corroboration of the abovementioned simulation analyses and theoretical findings is provided in Appendix C.

C. Other Practical Considerations
1) Resonance between L p(in) and C in : As shown in Fig. 14(a), it is observed both in simulation (Sim.) and (Expt.)that, with low C in , there will be an undesired increase in the output impedance the slow switching region L p(in) is small.This phenomenon to the resonance between L p(in) and C in , and can be explained as follows.As C in becomes smaller and smaller, the resonant frequency of L p(in) and C in , which can be given as f r(in) = gradually decreases.When the switching frequency approaches f r(in) , the input current I in will start to oscillate largely between positive and negative values, as illustrated in Fig. 14(b).Such oscillation can dramatically increase the input voltage ripple and therefore augment the voltage difference seen by C fly , thus leading to higher rms value of i C(fly) and higher output impedance.
It is worth noting that the abovementioned analysis is only an example of how the L p(in) -C in resonance can affect the input voltage ripple and output impedance of SC converters.Realistic input impedance networks can be more complex and can affect not only the performance but also the stability of power converters.Detailed effect analysis of the resonance between the source impedance and C in is out of the scope of this article and can be a good research topic for future works.
2) Effect of deadtime: As shown in Fig. 15(a), at very high switching frequency (i.e., beyond several MHz), a practical deadtime t d of several ns can lead to an unexpected increase in output impedance.This effect can be accurately captured by the proposed model by introducing the effective duration of conduction given in (7).
As illustrated in Fig. 15(b), the average value of i C(fly) in each phase should be the same no matter how long the deadtime is.However, with longer deadtime, the conduction duration of i C(fly) will become shorter, which leads to a higher rms value and thus higher conduction loss.This indicates that deadtime is also a factor that impedes increasing f sw in practice, apart from higher switching loss.
3) Multiphase interleaving: As discussed in [21], [27], for integrated SC converters, there is usually no penalty for multiphase interleaving.In multiphase interleaved SC converters, the flying capacitor(s) of one SC converter unit can serve as the terminal capacitor(s) for other units.Therefore, with sufficient interleaved phases, no explicit terminal capacitors are needed so that the majority of die area can be used to implement the flying capacitance.
The application of the proposed output impedance model to multiphase interleaved SC converters is out of the scope of this article and can be a worthwhile topic for future studies.Discussions on how to capture the effect of interleaving can be found in [21].

D. Design Guidelines
1) Size of the input capacitance: Since an insufficient input capacitance can increase the output impedance and harm overall efficiency, C in should be sufficiently large to ensure an approximately ideal input behavior.In particular, when class 2 capacitors are used as the input capacitor, special attention should be paid to ensure that C in is sufficient, since class 2 capacitors suffer from dc derating with applied input voltage.2) Size of the output capacitance: The output capacitance can be appropriately reduced to achieve both smaller physical size and lower output impedance (i.e., both higher power density and higher efficiency).However, C out should still be sufficiently large to satisfy the ripple constraint on the output voltage.3) Other practical considerations.i) In the slow switching region, the resonance between L p(in) and C in can cause an undesired increase in the output impedance.This can be avoided by ensuring sufficient C in or operating at a higher switching frequency.ii) At very high switching frequency (i.e., beyond several MHz), a practical deadtime t d of several nanoseconds can lead to a considerable increase in the output impedance and therefore can no longer be neglected in the analysis and design of SC converters.Further quantitative optimizations can be performed to find the best combination of C fly , C in , and C out to achieve the lowest output impedance within the given physical space limits and voltage ripple constraints.

V. APPLICATION TO ARBITRARY SC TOPOLOGIES
In this section, we apply the proposed modeling and analysis methodology to four commonly used SC topologies: seriesparallel, Fibonacci, doubler, and Dickson topologies, as shown in Fig. 16.These four examples are provided here to demonstrate the applicability of this model to arbitrary SC topologies.The set of converters considered in this section is limited to two-phase SC converters operating at 50% duty cycle.In the following examples, for simplicity, all flying capacitors have the same capacitance C fly = 10 μF, and all switching devices have the same ON-state resistance R on = 10 mΩ.

A. Model Application to Arbitrary SC Topologies
As has been mentioned in Section II-A, the circuit model shown in Fig. 4 can capture arbitrary SC topologies with suitable topology-dependent parameters.Therefore, the key step of applying the proposed model to an arbitrary SC topology is to obtain the equivalent capacitance C k and equivalent resistance R k in each phase.There are two cases: a) the simple case where C k and R k can be directly acquired by inspection, and b) the general case where the model parameters have to be carefully derived.
1) Simple case: Apart from the 2-to-1 SC topology, the seriesparallel topology is also an example of the simple case.Take the 4-to-1 series-parallel topology illustrated in Fig. 16(a) as an example-the model parameters of the series phase (i.e., phase 1) are C 1 = 1 3 C fly and R 1 = 4R on , and those of the parallel phase (i.e., phase 2) are C 2 = 3C fly and R 2 = 2 3 R on , which can be obtained from the equivalent circuits shown in Fig. 16(a) by inspection.
2) General case: In more general cases, C k and R k cannot be directly obtained by inspection from the equivalent circuits but Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
have to be carefully derived according to the invariance of the SSL and FSL output impedance.
On the one hand, with ideal input and output, the asymptotic SSL and FSL output impedances of two-phase SC converters have been given in [18] as in which C fly,i is the value of flying capacitor i, R on,i is the ON-state resistance of switch i, and a c,i and a r,i are the charge multipliers of capacitor i and switch i, respectively.
On the other hand, according to the proposed model, the output impedance of an SC converter with ideal input and output is given by (10).By performing the model approximation introduced in Section IV-A, the asymptotic SSL and FSL output impedances of (10) can be obtained as The SSL and FSL output impedances in ( 15) and ( 16) should be the same, and therefore we get Splitting (17) into each phase yields where δ i,k equals 1 when switch i is ON in phase k and equals 0 when it is OFF in phase k.
To take the effect of finite C in into consideration, we need to make further modification to C 1 (i.e., the C k value in case 1 of Fig. 4).Denote the charge multiplier of C in as a c,in , which is defined as the ratio of the charge transferred in C in in one phase to the total charge delivered to the output during a full switching period.For two-phase SC converters operating at 50% duty cycle, the charge transferred in C in in one phase is Thus, a c,in can be obtained by inspection as Similar to the flying capacitors, the contribution of the input capacitor to the SSL output impedance is proportional to a 2 c,in /C in , which has the same mathematical form of R SSL in (15).Therefore, compared to the situation with ideal input, due to the existence of finite C in , the contribution of phase 1 (case 1 in Fig. 4) to R SSL is increased by This means that we can incorporate the effect of C in in the model by modifying the C 1 in (18) with the factor f 1 as while still mathematically assuming ideal input in the calculation.Note that here we do not assume C in to be physically infinite but only introduce a mathematical simplification.In addition, note that since C in is hard-charged in phase 1 and soft-charged [37] by L p(in) in phase 2, it only leads to a greater contribution of phase 1 to R SSL but has no influence on the contribution of phase 2 to R SSL , which means only C 1 needs to be modified while C 2 does not.
To sum up, there are four steps to apply the proposed model to arbitrary SC topologies as follows.
1) Calculate the model parameters C k and R k with (18).
3) Substitute C 1 and C 2 into the case 2 of (3) to calculate C k(eff) and p k for each phase.4) Substitute C k(eff) , p k , and R k into (8), and calculate R out .Fig. 17 presents the output impedance of the four SC topologies shown in Fig. 16 with various terminal capacitances.The comparison between modeling and simulation results in Fig. 17 demonstrates the accuracy of the proposed output impedance model in different SC topologies with various terminal capacitances.Note that the proposed output impedance model is widely applicable to arbitrary SC topologies with practical C in and C out values but can be inaccurate in extreme scenarios that are not usual in practical applications, such as when C out is less than C fly .

B. Effect of Terminal Capacitances
As can be observed in Fig. 16, qualitatively speaking, the terminal capacitances exhibit the same effects on output impedance in these common SC topologies as in the 2-to-1 SC converter analyzed in Section IV-the insufficiency of C in leads to higher output impedance while smaller C out helps reduce output impedance.
Quantitatively speaking, we can notice that C out is more influential in the slow switching region while C in has a stronger effect at higher frequency around the knee of the output impedance curve.
It can also be observed that the effect of C in is weaker in these four SC topologies in comparison with the 2-to-1 SC converter.In the four SC topologies shown in Fig. 17, the output impedance with C in = C fly is very close to that with C in = 10C fly .SC topologies with higher conversion ratio generally have smaller equivalent capacitance (C k ) in the phase where the input terminal is connected to the source (i.e., case 1 in Fig. 4).Given that Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.the output impedance is dependent on the series capacitance of C in and C k , C in needs to be smaller to make the same impact on the output impedance of SC topologies with higher conversion ratio.This is a favorable feature, which means that smaller C in can be sufficient to ensure an approximately ideal input behavior in SC converters with higher conversion ratio.

VI. CONCLUSION
This article proposes a general modeling and analysis methodology that is able to characterize the effect of finite terminal capacitances on the output impedance of SC converters.A general output impedance model is derived and verified by circuit simulations and experimental measurements from a 2-to-1 SC converter prototype with less than 8% relative error.It is revealed that larger C in is favorable for efficiency improvement.On the contrary, smaller C out can help reduce output impedance, which contributes to both higher efficiency and higher power density, although C out should still be sufficiently large to satisfy the ripple constraint on the output voltage.In addition, C out is quantitatively more influential in the slow switching region while C in has a stronger effect on output impedance in the fast switching region, especially around the knee of the output impedance curve where SC converters typically operate.Finally, we demonstrate the applicability of the proposed modeling and analysis methodology to arbitrary SC topologies with four examples of commonly used SC converters.
This work provides an analytical tool for future investigations, such as design optimizations of SC converters with physical space limits and voltage ripple constraints.

APPENDIX A DERIVATION OF THE GENERAL OUTPUT IMPEDANCE MODEL
and Then so that the transferred charge in phase k can be calculated as On the other hand, q k and I out can be expressed as where q out is the total transferred charge to the output in a switching cycle.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
Substituting ( 6) and ( 27) into ( 26) yields the relationship between qk and q out as qk = âk q out (28) in which the coefficient âk has been given in (9).Substituting ( 23) and ( 28) into (24) yields ) Then, substituting ( 27) and ( 29) into (30) yields the expression of Rout that has been given in (9) as (31) Substituting ( 25) and ( 30) into (3) yields Additively combing (32) over all phases and substituting the summation into (1) and ( 2) yields the final expression of R out that has been given in (8) as ( For simplicity, here we consider a two-phase SC converter with 50% duty ratio and negligible deadtime (i.e., T 1(eff) = T 2(eff) = 1 2f sw ).Substituting (34) into (8) yields the contribution of phase k (k = 1, 2) to R out as (35) Substituting the topology-dependent parameters mentioned in Section III-B and additively combing the components in all phases yields the SSM and FSM for the 2-to-1 SC converter that has been given in (12) and (13).and C out values.The experimental waveforms were measured from the hardware prototype presented in Figs. 5 and 6.Current sense resistor voltages v RCS3 and v RCS4 were measured to obtain the current through the flying capacitor i C(fly) as As can be seen in Figs.18-20, the simulated and experimental waveforms are in excellent agreement.In addition, the waveforms presented in Figs.18-20 qualitatively match those in Figs. 12 and 13.The comparison between Fig. 18 and Fig. 19 shows that a smaller C in leads to a larger voltage difference seen by C fly (V C(in) − V C(out) − V C(fly) ), which results in higher rms and peak-to-peak values of i C(fly) , as listed in Table V and thus higher output impedance.Similarly, the comparison between Fig. 18 and Fig. 20 shows that the output voltage (V C(out) ) is able to follow V C(fly) when C out is smaller.As a results, i C(fly) drops faster and thus has a lower rms value as listed in Table V, which contributes to less power loss and lower output impedance.

Manuscript received 14
April 2023; revised 3 July 2023 and 19 August 2023; accepted 25 August 2023.Date of publication 18 September 2023; date of current version 19 April 2024.An earlier version of this paper was presented at the 2021 IEEE Applied Power Electronics Conference and Exposition (APEC) with the same title.This manuscript includes more detailed analyses, enriched design guidelines, and further explanations for the applicability of the proposed model to arbitrary SC topologies.Recommended for publication by Associate Editor S. S. Lee.(Corresponding author: Robert C. N. Pilawa-Podgurski.)

Fig. 1 .
Fig. 1.General steady-state model of an SC converter.(a) Idealized input and output.(b) Practical input and output.(L p(in) : the parasitic source inductance).

Fig. 2 .
Fig. 2. Output impedance of a 2-to-1 SC converter with different terminal capacitances.(a) Schematic drawing of the 2-to-1 SC converter.(b) Output impedance curves with different C in and C out .(C fly = 10 µF, R on = 10 mΩ).

Fig. 3 .
Fig. 3. Complete circuit model of an SC converter with finite C in and C out .(a) Case 1: the input terminal is connected to the source.(b) Case 2: the input terminal is grounded.

Fig. 4 .
Fig. 4. Simplified circuit model of an SC converter with finite C in and C out .(a) Case 1: the input terminal is connected to the source.(b) Case 2: the input terminal is grounded.

Fig. 7 .
Fig. 7. Output impedance of the SC converter with various C in .(C out = 5C fly ) (a) Comparison between the output impedances predicted by the proposed model (Model) and simulated by PLECS (Sim.).(b) Comparison between the output impedances predicted by the proposed model (Model) and measured from the prototype (Expt.).(c) Relative error of modeling results with respect to experimental measurements calculated with (11).

Fig. 8 .
Fig. 8. Output impedance of the SC converter with various C out .(C in = 5C fly ) (a) Comparison between the output impedances predicted by the proposed model (Model) and simulated by PLECS (Sim.).(b) Comparison between the output impedances predicted by the proposed model (Model) and measured from the prototype (Expt.).(c) Relative error of modeling results with respect to experimental measurements calculated with (11).

Fig. 10 .
Fig. 10.Effect of C in on output impedance.(Assuming ideal output) (a) Normalized output impedance R out /R FSL with various C in .(b) Ratio of R out to the output impedance with ideal input and output R out(ideal) .

Fig. 11 .
Fig. 11.Effect of C out on input impedance.(Assuming ideal output) (a) Normalized output impedance R out /R FSL with various C out .(b) Ratio of R out to the output impedance with ideal input and output R out(ideal) .

Fig. 14 .
Fig. 14.Effect of L p(in) on the output impedance of the 2-to-1 SC converter prototype.(C in = 0.5C fly , C out = 5C fly ) (a) Output impedance with small and large L in .(b) Simulated waveforms of I in with small and large L in .(f sw = 100 kHz).

Fig. 15 .
Fig. 15.Effect of deadtime on the output impedance of the 2-to-1 SC converter prototype.(C in = C out = 5C fly ) (a) Output impedance with and without deadtime.(b) Simulated waveforms of i C(fly) with and without deadtime.(f sw = 10 MHz).
(b)  as an example-we can obtain the model parameters asC 1 = 2 3 C fly , C 2 = 3 2 C fly , R 1 = 11 4 Ron , and R 2 = 16 9 R on .With the C k and R k values, we can calculate the output impedance of SC converters with ideal input and output by substituting (

out = f sw k Êk I 2
out + f sw k R k I fk 2q k + I fk T k(eff) I 2 out = Rout + k R k p k 2a k − p k f sw T k(eff) .(33)APPENDIX B MODEL APPROXIMATION BY TAYLOR EXPANSION By Taylor expansion, the hyperbolic function coth(x) (x > 0) can be approximated as coth(x) ≈

Fig. 18 .
Fig. 18.Comparison between simulated and experimental waveforms when C in = C out = 5C fly .(a) Simulated capacitor voltage waveforms.(b) Experimental capacitor voltage waveforms.(c) Simulated voltage waveforms across current sense resistors.(d) Experimental voltage waveforms across current sense resistors.

Fig. 19 .
Fig. 19.Comparison between simulated and experimental waveforms when C in = 0.5C fly , C out = 5C fly .(a) Simulated capacitor voltage waveforms.(b) Experimental capacitor voltage waveforms.(c) Simulated voltage waveforms across current sense resistors.(d) Experimental voltage waveforms across current sense resistors.

Fig. 20 .
Fig. 20.Comparison between simulated and experimental waveforms when C in = 5C fly , C out = 0.5C fly .(a) Simulated capacitor voltage waveforms.(b) Experimental capacitor voltage waveforms.(c) Simulated voltage waveforms across current sense resistors.(d) Experimental voltage waveforms across current sense resistors.

TABLE II MAXIMUM
RELATIVE ERRORS OF THE APPROXIMATED SSM AND FSM IN (12) WITH VARIOUS C IN AND C OUT