Performance of the binary silicon system for ATLAS

We report on the results from a beam test of a binary silicon strip system proposed for ATLAS. The data were collected during the H8 beam test at CERN in 1995 and at a beam test at KEK in 1996. The binary modules tested had been assembled from silicon micro-strip detectors of different layout and from front-end electronics chips of different architecture. The efficiency, noise occupancy, and position resolution were determined as a function of the threshold setting for various bias voltages and angles of incidence. Interstrip effects were also evaluated using a high resolution telescope. The performance of a prototype detector module irradiated to a fiuence of 1.2 × 10 14 p/cm 2 is also characterized.

collected during the H8 beam test at CERN in 1995 and at a beam test at KEK in 1996. The binary modules tested had been assembled from silicon micro-strip detectors of different layout and from front-end electronics chips of different architecture. The efficiency, noise occupancy, and position resolution were determined as a function of the threshold setting for various bias voltages and angles of incidence. Interstrip effects were also evaluated using a high resolution telescope. The performance of a prototype detector module irradiated to a fluence of 1.2 × 10a4p/cm ~ is also characteri~.ed.

I n t r o d u c t i o n
We are proposing to simplify the readout of silicon detectors in the Semiconductor Tracking Detector (SCT) [1] of ATLAS [2] by using a binary readout [3], which records only the addresses of strips with pulse height exceeding a preset 0920-5632/98/$19.00 © 1998 Elsevier Science B.xZ All rights reserved. PII S0920-5632(97)00565-3 threshold value. Thus the pulse height is not directly available during data taking. It has been shown [4,5] that the distribution of pulse heights can be recovered by varying the threshold and measuring the counting rate, which is the integral of the pulse height spectrum. Likewise, the noise can be determined from threshold scans without beams. It is important to note that the primary parameters of interest for a tracking device are not the signal and noise, but the single channel efficiency and position resolution, and the noise occupancy.
Basic requirements on a binary silicon system for ATLAS include the ability to operate at the LHC bunch crossing rate of 40 MHz, the ability to sustain estimated total fluences of 1014p/cm 2, and a point resolution of about 20 microns. These requirements translate to maximum noise occupancies of approximately 10 -a per channel and a high efficiency (>99%).
In the following, we report on the results from the 1995 ATLAS beam test [6,7] in the H8 beamline in the CERN North Area. We also report on the results of a beam test [8] carried out at KEK in 1996. Previous beam tests at KEK [5] have shown low noise occupancy at the nominal threshold of 1 fC and good efficiency, even at higher thresholds. In the H8 beamtest, the use of a beam telescope with a resolution of a few microns allowed the investigation of the efficiency at a fine scale as a function of the interstrip distance.

Benrn Test Setup
During the 1995 H8 beam test, several silicon micro-strip modules with binary readout were tested. Fig. I shows the schematic of the setup during the September run: the x-y beam telescopes bracketed the binary modules, and allowed the determination of the location of tracks in the modules to within 2-3 microns in the horizontal and the vertical directions. Two of the binary modules, called UCSC and DDR2, were held fixed, while the central one, called ATT3, was mounted on a rotary stage and could be rotated about an axis parallel to the strips. The distance between the x-y hodoscope planes was about 80cm and the distance between the binary modules was about 5cm. The setup at KEK was similar, with the exception that the beam telescope consisted of anchored binary modules. are directly bonded to the front-end electronics (FEE). In addition, the hybrid, which carries the FEE and the data and control signals, is mounted across the detector strips in the approximate center of the 12cm silicon detector module. The modules combined SSC-style and more recently developed LHC-style detectors with different FEE. Two bipolar amplifier-comparator chips ("LBIC" and "CAFE') with peaking time of close to 20ns were used. The LBIC [9] was developed for AC-couphd SSC detectors, while the CAFE [10] chip was designed for operation with finite input current for use with ATLAS DCcoupled detectors. Two CMOS digital pipelines were used, the CDP128 [11], a clock-driven binary pipeline, and the DDR2 [12], a data-driven binary pipeline with data compression and data transmission protocol similar to the ATLAS protocol.
The silicon detectors tested were AC-coupled double-sided detectors [13] with 50pro pitch developed in Japan for the SSC and DC-coupled ATLAS-type 75pro pitch detectors [14] fabricated at LBNL. Both Kapton flex-circuit and ceramic hybrids were used.
The teadouL newly developed for this test, is based on Digital Signal Processors (DSP's) utilizing a 40 MHz clock and designed to allow a data In addition to rotation scans, two parameters were varied to map out the detector performance: the detector bias voltage (Vbias) and the threshold voltage of the on-chip comparators (Qthr). The results from the threshold scans were used to determine the pulse height spectrum. The data at different rotation angles helped us to understand the effects of finite track crossing angles.

Noise Occupancy
The noise occupancy was measured as a function of the threshold voltage to determine the rms noise. This was done before and after the run using the full DAQ. Channels which were obviously noisy were removed from the data. The occupancy per channel as a function of Qt~hr is shown in Fig. 2. Since neither of the pipelines are edge-sensing and since the comparator chips have different output widths, the occupancy data have been corrected for the number of effective time slices sensed by the pipeline.
The occupancies are approximate Gaussian functions of the threshold voltage. The slope is a measure of the noise variance. We observe the expected dependence of the noise on the strip length (12cm vs 6cm). Extrapolating the noise occupancies to Qthr:l fC gives a noise occupancy of 0.8 x 10-4(~rn ~ 1640e-) for the ATT3 module and 1.5 × 10-4(~n ~ 1706e-) for the UCSC module. After the H8 test, it was discovered that the CAFE chips were operated at a non-optimal power setting. Subsequent measurements at the KEK testbeam revealed a noise occupancy (at the nominal Qthr=l fC) of <= 10 -s.

Data Analysis
After aligning each module with the tracking program, only events with one "good" track were analyzed. Good tracks were defined as tracks with a X 2 probability Px ~ >1% which intercept the fiducial region of a detector module.
Clusters were formed by joining a~acent hit strips up to :1:2 strips away from the expected track impact point. The cluster position was assigned to the geometric center of the cluster. Events with clusters close to known noisy or dead strips were rejected. The surviving events were then used in the efficiency and resolution measurements.
the edge of the strips, where tracks tend to form multi-hit clusters.

E f f i c i e n c y vs. I n t e r s t r i p P o s i t i o n
The efficiency for the p-side detector read out with the DDR2 chip is shown in Fig. 3 as a function of the interstrip position. The interstrip position is calculated as the crossing point of a track in the detector in one unit of strip pitch. It is defined such that the strip-to-strip boundary is centered at 0.5.
As expected, as Qthr iS increased, the efficiency starts to degrade at the strip edges. This is due to a reduction in the effective pulse height due to charge sharing between strips. Nevertheless, at the nominal operating threshold (Qthr--1 fC), the efficiency is well over 99% at the strip edge. The overall efficiency is also > 99% at a ~thr 40% higher than nominal. It is 50% close to 3.5 fC, the median of the binary Landau distribution.  o  lfC  o  1.86fC   ,  ,  ,  I  ,  ,  ,  ,  ,  ,  I  ,  ,  ,  I  shows the rms resolution at Qthr~-I fC for multihit clusters and for all clusters in the DDR2 module. An improvement in the resolution due to charge sharing is evident, but the usefulness of charge sharing in a binary system is limited to

E f f i c i e n c y a n d R e s o l u t i o n vs. Vbiu
Since n-on-n detectors deplete from the ba~kside, the collection of charge might be less efficient at lower bias voltages than at higher ones. The UCSC module depletes at about 70V. This module was operated at a Vbias of 100V and 200V. The efficiency was found to be close to 100% around the nominal Qthr of 1 fC and to have a median of 3.5 fC, confirming earlier testbeam results [4,5]. Fig. 5 compares the efficiencies at the edge of the strips at the two bias voltages . The strip edges are expected to be more sensitive to the increase in charge collection efficiencies due to h i g h e r Vbias. In fact, the data are virtually identical at the nominal threshold of 1 fC and it is only at 1.7 fC that there is a noticeable effect.

D e p e n d e n c e o n R o t a t i o n A n g l e
The data of the ATT3 module were taken at constant Vbi~, but at varying rotation angle. The n-on-p detector has a depletion voltage (Vdepl) of about 140V, and was operated at close to 80V due to limitations in one of the power supplies. With the junction on the n side, this mode of operation corresponds to an inverted n-on-n detector operated at partial depletion, which is an option for the ATLAS SCT in case of unexpectedly high radiation levels. Fig. 6 shows the rms resolution and the hit multiplicity for three rotation angles at Qthr:] fC-Due to increased charge sharing, the mean pulse height, i.e. the ~thr vKlue at the median of the efficiency curve, decreases as the rotation angle increases. This, in turn, increases the charge multiplieity and improves the resolution. However, the efficiency is well above 99% for thresholds below 1.2 fC and for MI rotation angles.

Irradiation Studies
One of the modules tested during the KEK testbeam in 1996 (ATT4 module) had been irradiated to a fluence of 1.2 x 10a4protons/cm2 (at 12 GeV). Unfortunately, some of the post-irradiation history of the module included unwanted wa~mup periods resulting in a full depletion voltage higher than planned (~ 280V). Fig. 7 shows the noise occupancy vs. efficiency curves for the irradiated modules at VbiM----V'depl and at ],rbiMm-55~0Vdepl. At approximately full-depletion voltage and Qthr----1 fC, the efficiency is over 99% and the noise occupancy is slightly above 10 -4 . At approximately hMf of full-depletion voltage, the efficiency drops only to 96%. Fig. 8 shows the mean pulse height (MPH) as a function of the bias voltage for the irradiated and the non-irradiated modules. It is interesting to note that, even though there is a noticeable degradation in the MPH for the irradiated module, the MPH is safely above the nominal operating threshold of 1 fC. This may provide a reasonable safety margin (or "headroom"), in terms of efficiency and noise, in order to operate in the LHC environment.   Figure 8. The MPH as a function of Vbi~.

Discussion and Conclusion
Beam tests performed with various detector modules using a binary readout show that such a system may provide reasonable performance in the LHC environment. The KEK and CERN beam tests presented here included studies of efficiency, noise occupancy, incidence angle, and interstrip effects on various detector modules and using different architectures. At the nominal operating threshold of 1 fC, good efficiency was found for tracks inclined up to 14 degrees. The efficiency of n-side on a-bulk detectors was found to have a marginal dependence on Vbiu once the detector is depleted. Furthermore, an irradiated non-n detector, operating at about and well below its depletion voltage had just a moderate degradation in performance.
From these data, it can be concluded that a realistic silicon strip binary system could have a headroom of 20-50% in Qthr for an efficiency > 99% and a noise occupancy of ~ 10 -4.
The ATLAS binary beamtest program, for the past two years, has been focused in proving the feasibility of such a system in the LHC environment. Now the focus has shifted [15] to providing the final performance parameters in preparation for a final technology choice within the ATLAS Collaboration.

A c k n o w l e d g e n t s
This work was supported by the UK Research Council, the US Department of Energy, and the US-Japan Scientific Cooperation Program.