The Symmetric Dual Inductor Hybrid Converter for Direct 48V-to-PoL Conversion

This work introduces the symmetric dual inductor hybrid (SDIH) dc–dc converter topology, which is suitable for large conversion ratios where regulation is required, such as direct 48 V to point-of-load (PoL) applications. A Dickson-type switched capacitor network is used to effectively produce two interleaved pulsewidth-modulated (PWM) outputs with a greatly reduced voltage amplitude relative to the input voltage, allowing the subsequent magnetic volume to be reduced while retaining modest switching frequencies. Distinct from related variations, part count is significantly reduced while both even and odd order switched capacitor networks can be used with straightforward split-phase control; allowing either network type to achieve complete soft-charging of all flying capacitors. Additionally, charge flow is uniformly distributed through all elements, with equal capacitor and inductor values being preferred. Subsequently, this topology is expected to simplify component selection, improve electrical and thermal performance, and reduce cost. Furthermore, analysis is presented that calculates precise phase durations without making small ripple assumptions, revealing up to a 75% timing error in cases where either inductor or capacitor ripple is ignored. Finally, a discrete prototype validates this analysis and demonstrates very high measured power densities of 1029, 754, and 663 W/in$^{3}$ for 48 V input and regulated output voltages of 3, 2, and 1 V, respectively, while switching at a frequency of 750 kHz.

Switches requiring mirrored split-phase switching [7] are marked with an asterisk (*), assuming all flying capacitors are equal in size.
significant effort has been put into improved power delivery techniques, with power density and efficiency being key metrics used in surveying eligible converter architectures.One common solution is to use a two-stage approach whereby a 48 V bus is first converted to an intermediary voltage (e.g., 12 V) before being stepped down to ∼1 V using voltage regulation modules (VRMs) [2], [3], [4], [5], [6].
Alternatively, direct 48 V to point-of-load (PoL) architectures have been proposed with reduced cost and further improved power conversion efficiency and/or density expected.Of these direct approaches, transformer-based solutions have received much interest [8], [9].In addition, stacked composite structures (e.g., [10]) can further leverage soft-switching and partial power processing [11] by using a fixed ratio DCX stage-such as a resonant LLC-to perform the majority of voltage conversion, while simultaneously enhancing the output regulation range.
Separately, soft-charged [12] or "hybrid" switched-capacitor (HSC) networks, including that depicted in Fig. 1, also demonstrate very high performance [13], [14], [15], [16].This approach circumvents the slow switching limit (SSL [17]) and associated transient pulse inrush currents that typically inhibit purely capacitor-based converters from availing of capacitor's high energy densities [18].To do so, inductors are strategically placed into a capacitor network, preventing the occurrence of SSL transient pulses without inhibiting voltage conversion.As a result, flying capacitors can experience large voltage ripple for greatly improved energy utilization [19] and reduced converter volume while preserving high efficiency.Moreover, the inductive elements are typically subjected to greatly reduced voltseconds when compared with purely inductor-based conversion (e.g., buck/boost) and so can also be reduced substantially in size [20].
At fixed conversion ratios, several HSC designs are resonant and can achieve zero-current or zero-voltage switching (ZCS/ZVS) conditions similar to the popular LLC converter [21], [22], [23].However, conduction and core losses typically dominate at heavy load, and so HSC's can alternatively be configured to operate with unipolar currents, including in continuous conduction mode (CCM), by placement of their inductors at the lowside terminal as opposed to within an internal tank structure [24], [25].As a result, rms currents can be reduced and magnetic core polarity need not be periodically reversed.In addition, this approach provides improved immunity to component mismatch without increasing circulating currents when switching at frequencies above resonance.Furthermore, the ability to interleave phase-shifted PWM outputs and use coupled inductors in regulating designs has positive implications for transient response and maximum achievable slew rate in PoL converters [26], [27].
The drawback of the HSC approach is typically viewed as the high complexity and component count, with added concerns about reliability and cost.However, as noted in [20], Dicksontype topologies can achieve best in class volt-amp switch utilization, signifying that while they may have an increased number of switches relative to more traditional architectures (e.g.buck, LLC, DAB), their net die area (in the case of a fully integrated solution) can be greatly improved.In addition, the proliferation of copackaged gate drive and power semiconductor modules has reduced design complexity [28], with fully integrated solutions improving reliability through use of a monolithic process [29], [30], [31], [32].Moreover, the improved performance of these designs may lead to improved reliability as a result of reduced thermal management requirements and lower overall operating temperatures [33], [34].
As such, direct 48-1 V conversion is a highly active area of research without a clear consensus on best topological approach.In this work we expand on [1] by further introducing an additional converter topology for consideration; the symmetricdual-inductor-hybrid (SDIH) converter, as depicted in Fig. 1.As will be discussed, it bears similarity to both the recently introduced dual-inductor-hybrid (DIH) converter [13] and the series-capacitor-buck (SCB) converter [35], with all three converters expressing the same volt-amp switch rating [17].However, as a result of its symmetry the proposed design achieves balanced charge flow through both of its inductors and all of its switches at both even and odd conversion ratios, simplifying design effort and improving component utilization.In addition, it has an interleaved high-side input: when compared with two Fig. 2. Series-capacitor-buck (SCB) topology, previously demonstrated in [35], [36], [37], and [38].Switches active during the primary two switching phases are color-coded red and blue.interleaved instances of either the DIH or the SCB convertersin order to yield identical line filtering requirements-the proposed SDIH topology requires significantly fewer parts.
The rest of this article is organized as follows.Section II contextualizes the evolution of the SDIH by first assessing both the advantages and limitations of the SCB and DIH topologies.Section III formally describes the proposed SDIH topology, highlighting its differentiating features and characteristics.Section IV presents-for the first time-the steady-state large signal (i.e., incorporating the effect of ripple) analysis required to calculate precise timing durations for "split-phase" clocking [7] in a regulating HSC converter; a clocking scheme that is necessary to ensure complete soft-charging of the flying capacitors in several of the most competitive HSC topologies, including both the DIH and SDIH proposed here.Dissimilar to prior work, this analysis does not make any small ripple assumptions and allows the full large signal operating points to be calculated accurately.We demonstrate that previous analysis using small ripple assumptions may result in up to a 75% error in phase timings.
Section V introduces the first SDIH hardware prototype, with subsequent measurements validating the preceding analysis.A subsequent revision is then used to showcase extremely high power densities.The second version is then compared against recent state of the art 48 V-to-PoL converter solutions.Section VI concludes this article.

II. PRIOR WORK
The SCB topology [35], [36], [37], [38], depicted in Fig. 2, is an HSC structure that has been commercialized in recent years [31] due to its excellent performance in high conversion ratio regulated applications.As a ladder or Dickson-type structure, it achieves among the best volt-amp switch stress and benefits from greatly reduced inductor volt-seconds as per fundamental HSC theory [20], [39].In addition, recent topological variations have also been proposed that tradeoff switch performance for improved passive component utilization [40], [41].Switch stress is minimized if the SCB is designed for regulation near its maximum switch duty cycle of 50%, resulting in largely two-phase operation, as color-coded in Fig. 2. Conversely, its Fig. 3. Two interleaved even-order DIH converters operating 180 • out of phase for reduced input filtering requirements.Switches active during the two primary phases are color-coded red and blue.Switches marked with an asterisk (*) must undergo split-phase switching to preserve complete SSL mitigation, assuming all flying capacitors have equal value.This arrangement can be consolidated into the proposed SDIH topology depicted in Fig. 1 by combining specific switches and inductors.conversion ratio may be increased by inserting additional tertiary phases within a switching period, during which odd numbered (as labeled in Fig. 2) switches only are activated.During these intervals, the flying capacitors remain static and conduct zero charge while the left side of all inductors are temporarily shorted to ground.By regulating the duration of these tertiary phases with respect to the two primary phases depicted, pulsewidthmodulated (PWM) regulation can be achieved.Additionally, as a result of charge conservation in the flying capacitors, current is balanced equally among all output inductors [42], provided that each inductor experiences the same PWM duty cycle.Furthermore, there are no sizing requirements imposed on the flying capacitors to avoid SSL losses, allowing the use of high density Class II multilayer ceramic chip (MLCC) capacitors that offer high energy densities but poor component tolerance [43].Moreover, at the cost of a further decreased duty cycle, the primary two phases of the capacitor network can be split into phase shifted subintervals, allowing each output inductor to operate with an interleaved fractional phase shift less than 180 • [35], [44], [45].While this approach may facilitate the effective use of interleaved coupled inductors for improved magnetic performance, the SCB is often operated with two predominant phases to increase the achievable duty cycle and subsequent switch performance, while simplifying control and resulting in the current ripple of every other inductor being in-phase, as in [36] and [38].
Recognizing this phase alignment, the DIH topology improves upon the SCB by lumping together both in-phase inductors and ground referenced switches, greatly reducing the overall component count.The resulting DIH topology-of which there are two interleaved instances depicted in Fig. 3-is largely equivalent to the SCB, retaining a highly competitive volt-amp switch stress rating and featuring a modestly improved magnetic utilization as a result of consolidated core material [46].To clarify this transformation, switches S 1 and S 5 in Fig. 2 are combined together to produce switch S L1 in Fig. 3, while switches S 3 and S 2N −1 in Fig. 2 effect switch S L,N +2 in Fig. 3.Then, since inductors L 1 and L 3 operate in-phase in Fig. 2, they are combined to form inductor L 1 in Fig. 3. Similarly, L 2 and L N in Fig. 2 combine to form L 2 in Fig. 3.As a result of this consolidation, the DIH requires N + 2 switches, versus the 2 N required by the SCB for an N th order HSC network.
However, dissimilar to the SCB-and as a result of the reduced inductor count-the DIH is subjected to finite flying capacitor sizing constraints in order to avoid SSL losses.Should capacitor values deviate from those prescribed, SSL losses will be reintroduced, but at a gradual rate commensurate with the degree of mismatch.An appropriate flying capacitor sizing scheme that allowed two primary phases to be retained was demonstrated in [47] for odd order capacitor networks only, however, this solution leads to diverging capacitor values and excessive passive volume for flying capacitor networks of order N > 6, as derived in [48].As initially noted in [13], a more effective solution is to set all flying capacitors equal in value and to instead employ the use of "split-phase" switching to avoid SSL losses [7], with [16] more recently demonstrating a preferred alternative split-phase control sequence for step-down applications.The split-phase technique involves the careful removal of specific flying capacitors from the conduction path part way through a primary conduction phase.That is, some flying capacitors only conduct charge for a subinterval of a primary phase, effectively splitting it into two distinct parts.As a result, full SSL mitigation is retained with minimal added clocking complexity or impact on switch stress.
Despite these advancements, odd ordered DIH converters still suffer from asymmetric current stress which leads to complications with component selection and thermal management.Furthermore, analysis calculating the timing durations of split-phase intervals has been presented, but has historically made zero ripple assumptions about either inductor current ripple, as in [7], or flying capacitor voltage ripple, as in [13].As will be demonstrated here, these assumptions can lead to significant timing errors when a converter is operated under large ripple conditions, as is desired for effective passive utilization.Subsequently, Section IV presents analysis that yields accurate split-phase control of a regulating HSC converter without making any small ripple assumptions.

III. PROPOSED SDIH CONVERTER
To arrive at the proposed topology depicted in Fig. 1, first consider two instances of the even-order DIH topology arranged in an interleaved manner with a 180 • phase shift, as depicted in Fig. 3. Here, all flying capacitors are assumed to be equal in value and switches S X,2 and S X,N +1 are marked with an asterisk, denoting their requirement for split-phase switching.Since both primary phase durations-including the split-phase intervals therein-are identical in an even-order DIH, switch pairs {S L2 , S R,N +1 } and {S R2 , S L,N +1 } can leverage the same split-phase control signal.Moreover, the timing of only one Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.split-phase event need be calculated in practice, with this interval copied through both primary phases.As a result, this arrangement does not add any control complexity relative to a single even-order DIH, while facilitating an interleaved high-side port for reduced input filtering requirements at V IN .
To reduce this configuration into the proposed SDIH topology depicted in Fig. 1, the circuit node at the drain of S L1 is merged with that at the drain of S R,N +2 , with both switches combining into a single device, labeled S L1 in Fig. 1.A similar reduction is made for S R1 and S L,N +2 .As a result, the overall switch count is reduced by two.In addition, since inductor pairs {L 1 , L 3 } and {L 2 , L 4 } are now in parallel, they can be combined and the inductor count is halved, further benefiting from the scaling argument posed in [46].To contextualize this reduction in component count, Table I lists the number of switches and inductors required by the proposed SDIH in comparison with two interleaved instances of both the DIH and SCB, where the latter two are interleaved to ensure identical input and output filtering requirements for fair comparison.Here, the proposed SDIH topology requires significantly fewer parts, with its reduced switch count additionally alleviating gate-drive and level-shift requirements.
While even-order DIH networks are depicted in Fig. 3, oddorder DIH networks experience asymmetric phase control with split-phase switching only required during one of the two primary phases.In this case, the second interleaved DIH would require an independent set of 180 • shifted control signals, adding to the control complexity.In addition, as noted in [47], switches S X1 and S X,N +2 would conduct unequal charge, leading to a current imbalance between the DIH's two inductors.Fortunately, these complexities do not extend to the merged SDIH structure, where complete symmetry is imposed for both odd and even order capacitor networks.As a result, control effort is minimal for any capacitor network order N , and component selection is simplified with all mirrored components carrying identical rms currents.
Fig. 4 depicts the intended phase progression for the SDIH topology, including two additional regulation phases, 2 and 4, in which both inductors are grounded.Primary phase 1 is split into subintervals 1A and 1B to facilitate split-phase constraints, while phases 3A, 3B, and 4 are mirrored copies of phases 1A, 1B, and 2, respectively.As such, only three time intervals need be calculated to define a given operating point (versus the two required by a basic buck converter operating in continuous conduction mode).
As a regulating converter operating in continuous conduction mode, hard-switching losses are expected.However, similar to a conventional buck converter, low-side switches S L1 and S R1 may achieve ZVS turn-ON upon commencement of phases 2 and 4, respectively, provided that sufficiently long preceding deadtime intervals are implemented.During these deadtime intervals, current in L 1 and L 2 serves to discharge v SW,1 and v SW,2 , respectively, to 0 V. Simultaneously, associated high-side switches are also partially discharged, leading to improved highside related switching losses.Switching losses are otherwise addressed using conventional means and are not elaborated on further in this work.

IV. STEADY-STATE ANALYSIS
This section details the steady-state analysis required to derive the appropriate duration of each phase interval, subject to a given operating point.Similar analysis was conducted in [7], which assumed zero inductor current ripple, and [13], which assumed zero flying capacitor voltage ripple.The analysis presented here does not make any small ripple assumptions and its improved accuracy is validated in hardware in Section V. Similar to previous efforts, lossless conversion is assumed, with the impact of ohmic voltage droop in a high efficiency design deemed to have a negligible impact on relative split-phase timing relationships, although the conversion ratio may need some compensation in practice.Continuous forward conduction in both inductors is also assumed, although the boundaries of both discontinuous conduction mode (DCM) and maximum capacitor ripple will be highlighted.In addition, only one half of the SDIH's operation need be considered as a result of its complete symmetry.That is, only waveforms i L,1 (t) and v SW,1 (t) are assessed, with the understanding that i L,2 (t) and v SW,2 (t) are identical bar a 180 • phase shift.All flying capacitors and inductors are set equal to C 0 and L, respectively, for simplified part selection, minimal split-phase complexity, and uniform loss distribution.
In order to account for both large signal flying capacitor voltage ripple and inductor current ripple simultaneously, second order LC networks must be considered.Fig. 5 depicts the lumped equivalent capacitance, as a function of N , presented to inductor L 1 during phases 1A and 1B.For the remaining phases L 1 is connected across V OU T and sees a linear decrease in current.Fig. 6 depicts the associated generalized waveforms for both inductor current i L1 and switch node voltage v SW,1 .Also annotated in Fig. 6 is the natural frequency response during 1A and 1B ) Additionally, we note the general expressions for an arbitrary LC tank that account for initial inductor current and capacitor voltage Using ( 3) and (4), general expressions for i L1 (t) and v SW,1 (t) accounting for initial current and voltage can be expressed as during interval {0, t 1 }, and Next, we obtain expressions for the instantaneous value of v SW at each phase transition (v SW (0), v SW (t 1 ), and v SW (t 2 )), temporarily ignoring the in-phase transitional dynamics described by ( 5)- (10).To do so, first charge flow analysis similar to that presented in [48] is applied to the flying capacitor network depicted in Fig. 4 to deduce the relative charge flow through all flying capacitors, using the input charge q IN provided by V IN Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
each period as a normalizing charge quantity.That is where f SW is the converter's switching frequency.Note that since all flying capacitors have been set equal to C 0 , any branch containing two capacitors connected in series expresses twice the net impedance-and conducts half as much charge per unit time-as a branch containing a single capacitor.In addition, since each flying capacitor conducts the same net quantity of charge per period, the split-phase transition between 1A and 1B occurs once half of the total charge required by each series connected branch has been conducted.Using this result, the areas X 1 , X 2 , and X 3 , depicted in Fig. 6 can be generally expressed as where X 3 is obtained by subtracting X 1 and X 2 from the total charge conducted by L 1 each period.In addition, an expression for the midrange dc voltage stored on each flying capacitor is obtained using the large signal KVL analysis presented in [48, Sec.VI] where i denotes capacitor numbering as depicted in Figs. 1 and 4, and ΔV is half the total peak-to-peak voltage ripple expressed on each flying capacitor i.e., each flying capacitor is exercised over the voltage range V C X,i ± ΔV .Subsequently, expressions for the instantaneous value of v SW at each phase transition can be obtained via KVL, where (15) and ( 16) ensure that large signal voltage ripple on the flying capacitors is accounted for Having obtained expressions (1)-( 19), the converter's steadystate operating point and phase timings, t 1 and t 2 , can be accurately solved for as a function of input parameters V IN , V OU T , N , f SW , I OU T (or I IN ), C 0 , and L. However, as a result of nonlinear trigonometric functions, a closed-form solution is nontrivial.Instead, this system of equations is solved numerically with relative ease.One straight-forward numerical approach is to set an initial guess for i L,1 (0) and use this value to progress through ( 5)- (10), using ( 17)- (19) to determine when a transition to a subsequent phase interval can occur.This results in a value for i L,1 (T ) at the end of a switching period.This process can then be repeated, adjusting the initial i L,1 (0) value, until i L,1 (T ) = i L,1 (0), signifying the arrival at a periodic steady-state solution.Conveniently, the full i L,1 (t) waveform is obtained, assisting with any subsequent loss estimation.Also plotted is v SW (t 2 ) which is the lowest driving voltage applied to L 1 throughout phases 1A and 1B.As flying capacitor voltage ripple increases with load, v SW (t 2 ) tends toward 0 V. Should v SW (t 2 ) reach 0 V, reverse conduction in switch S L1 is likely, representing an equivalent capacitor induced DCM.
To compare this approach with prior analysis using small ripple approximations, Fig. 8 plots the calculated steady-state waveforms of v SW,1 and i L,1 under three sets of assumptions: first, assuming zero inductor current ripple (green), as in [7].Here i L,1 is constant and v SW,1 changes with a constant slope.Second, assuming zero capacitor voltage ripple (red) [13], where v SW,1 is flat and equal to V IN /N during phases 1A and 1B, and i L,1 changes linearly due to a constant voltage being applied to L 1 during each phase.Third, assuming full ripple on both capacitors and inductor (this article).Here, both i L,1 and v SW,1 follow sinusoidal segments during phases 1A and 1B.An operating point is chosen at which both large flying capacitor voltage ripple and inductor current ripple are expected; this both emphasizes the differences between each case and maximizes given passive component utilization.The area under the curve of i L,1 during phases 1A and 1B (X 1 and X 2 in Fig. 6) is identical between the three cases, ensuring ( 12)-( 14) are always satisfied.However, the calculated phase timings required in order to meet these constraints varies depending on which set of assumptions are used.
For example, when using this work's full ripple assumptions, phase 1B is expected to finish much sooner than predicted by either of the other two cases (shorter t 2 ).Furthermore, while the time ratio of phase 1B to phase 1A is approximated well when only inductor ripple is accounted for, as in [13], the absolute duration of both phases is 19% longer than that predicted by the full ripple case.As a result, the converter's output voltage is expected to be be higher than intended.Moreover, the absolute duration of phase 1B deviates by up to 75% when comparing the full ripple case with that ignoring inductor current ripple.

V. EXPERIMENTAL RESULTS
A hardware prototype of an N = 6 SDIH converter, photographed in Fig. 9, was constructed on a 4-layer 0.6 mm thick PCB to validate both the functionality of the proposed topology and the improved accuracy of the preceding full ripple analysis.Power was delivered to the gate-drivers of all 14 switches using cascaded bootstrapping [49], as illustrated in Fig. 10.Here, charge is handed from the gate driving circuitry of switch S X,i to that of switch S X,i+1 , via bootstrapping diode D BT during the ON-time of switch S X,i .This approach tolerates an accumulation of successive diodes drops and Fig. 10.Schematic of the level-shifted gate driving circuitry and cascaded bootstrap power delivery using an 8 V supply, depicted for switches S L1 − S L3 .This same scheme is used for all primary switches S L1 − S L7 and S R1 − S R7 .may be improved through the introduction of synchronous bootstrapping [50] at the cost of added complexity.Table II lists all of the components used.A HFS9003 clock generator was used to provide clock signals to the input of each level-shifted gate driver.Despite their reduced energy density relative to Class II dielectrics, Class I (C0G) fly capacitors were used here for both their fine matching tolerance, stability, and low loss when subject to large voltage ripple [43], [51].
Two different pairs of inductors were implemented: larger stable ferrites (1 μH) were implemented when validating the preceding timing analysis since this choice minimizes the effects of parasitics and probing and omits the added complexity of inductance derating with load (applicable to Figs. 12-14).Conversely, small 150 nH composite core inductors were used to demonstrate this topology's capability for very high power densities and improved transient response at an increased switching frequency of 750 kHz.
Fig. 11 depicts the high density revision's volume breakdown where total converter volume is defined as a best-fit cuboid encompassing the entire design, including input and output capacitors.To begin, Fig. 12 generally illustrates the necessity for splitphase switching in applicable topologies when flying capacitors are operated with large ripple for improved utilization.Here, the voltage on each left-sided flying capacitor is plotted across a full switching period in steady-state.While not plotted for clarity, all right-sided flying capacitors express identical waveforms, albeit with a 180 • phase shift.Smooth voltage transitions on the flying capacitors implies complete soft-charging and full mitigation of SSL losses.In contrast, when split-phase operation is disabledand phases 1B and 3B are effectively removed-abrupt step changes in flying capacitor voltages are observed, signifying the reintroduction of pulsed inrush currents and SSL loss.As a result, measured converter efficiency is severely degraded from 87.1% to 82.7%.
Next, the same operating point as that depicted in Fig. 7 was recreated in hardware.Fig. 13 illustrates operation both at the minimum boundary inductor current before DCM and at the point of maximum flying capacitor voltage ripple while using phase durations calculated without making small ripple assumptions.Here, both i L,1 (t) and i L,2 (t) current waveforms reach 0 A when I OU T = 7.5 A, while both v SW,1 (t) and v SW,2 (t) waveforms swing to 0 V for I T = A.These operating points align precisely with that predicted by Fig. 7.
To further motivate the presented full ripple analysis in contrast to simplified approaches, the operating point described in Fig. 8 was also recreated.Fig. 14 plots measured v SW,1 (t) waveforms for the converter operating with both: 1) full ripple timings; and 2) timings assuming flying capacitor ripple only.When inductor current ripple is neglected, the required duration of phase 1B is greatly overestimated.Subsequently, unintended reverse body diode conduction is observed for a significant portion of the total switching period.Conversely, the full ripple analysis provides more accurate control and removes the unintended freewheeling interval and associated reverse conduction loss.Subsequently, measured converter efficiency is increased from 83.9% to 87.1%.
When phase timings accounting for inductor ripple only are used instead, the relative timing of phase 1A to 1B is approximately accurate, as noted in Section IV, and correct soft-charging operation is preserved.However, as a result of the error in absolute duration of phases 1A and 1B, the output voltage increases above its intended operating point of 3.3 V (not depicted).
Finally, L 1 and L 2 were replaced with the smaller 150 nH inductors and the converter's switching frequency was increased to 750 kHz to extend its maximum achievable output power.Fig. 15 plots measured efficiency versus output power at output voltages of 3, 2, and 1 V, and omits a gate drive power loss of 1.62 μJ per switching period to facilitate a fair comparison with data reported in prior art.In addition, Figs.16 and 17 depict transient output voltage steps from 1 V-to-2 V and 2 V-to-1 V, respectively, for a constant load current of I OU T = 10 A. Both transitions reach their target values within 1.6 μs, as defined by 10%-90% thresholds.For a 48 V input and N = 6, each inductor is subjected to a nominal driving voltage of either   similar methods finding use in systems employing dynamicvoltage-scaling (DVS) (e.g., [52]).Alternatively, nonlinear feedback control building on the large-signal analysis presented in Section IV may be implemented, but is beyond the scope of this work.We note that classical control using small-signal approximations and local linearization does not capture the large-signal effects modelled in Section IV, and subsequently may not ensure complete soft-charging of the flying capacitors under large ripple conditions.Further improvement to transient response in a future prototype may be achieved through the use of coupled magnetics [53], as indicated by the inherent 180 • phase shift between inductor current waveforms.
Table III compares this prototype recent state of the art, demonstrating extremely high measured power densities with this design.This is despite the use of low density Class I dielectrics, which are being effectively operated with large ripple for very high energy density utilization.We note that for this first prototype, switches S L2−7 and S R2−7 were chosen for ease of implementation given their identical footprint to S L1 and S R1 , but are significantly oversized.As such, a future iteration may expect a reduction associated switching losses and provide more competitive efficiencies.Furthermore, while the presented full ripple analysis served to accurately assist with the determination of allowable operating range and clocking requirements, closed-loop adjustments to split-phase timings in response to changes in load was not performed.Moreover, the 150 nH composite core inductors used in this high density revision exhibit soft-saturation with increasing load.As of yet, closed-loop split-phase control that can compensate for both changes in load and passive derating has not yet been demonstrated, but is a subject of active research.

VI. CONCLUSION
This article demonstrates a new SDIH Dickson-type topology that is well suited for large regulated conversion ratios, such as 48 V-to-PoL applications.Due to the symmetry of the proposed topology, the high-side input sees interleaved current draw for reduced filtering requirements and charge flow is equally distributed through all mirrored components for simplified component selection and thermal management.In addition, all flying capacitors are fully soft-charged, circumventing the slowswitching-limit and allowing for increased voltage ripple and subsequent improved energy density utilization.Furthermore, this article presents analysis that yields accurate phase timing control by accounting for large-signal ripple on both flying capacitors and inductors simultaneously.While split-phase control is required, its complexity is minimal and a fixed cost that does not scale with capacitor network order (odd and even inclusive), provided that all flying capacitors are sized equally.
Finally, a 48 V-to-PoL discrete hardware prototype confirms expected operation of the proposed SDIH topology and validates the presented analysis.This prototype demonstrates very high power densities of 1029, 754, and 663 W/in 3 for regulated output voltages of 3, 2 and 1 V respectively, despite using calculated split-phase timings without active feedback.

Fig. 4 .
Fig.4.Periodic phase progression of the proposed SDIH converter (left to right) when optimized for step-down split-phase operation.Phases 1 and 3 are split into subintervals, A and B, to facilitate split-phase switching.The four switches requiring split-phase operation are marked with an asterisk (*) and reside only at the extreme ends of the switched-capacitor network, for all N ≥ 3, when all fly capacitors are set equal to C 0 .Charge flow through each flying capacitor is annotated and expressed relative to the total periodic input charge quantity q IN that is admitted during phases 1A and 3A.

Fig. 5 .
Fig. 5. Equivalent circuit states from the perspective of inductor L 1 .

Fig. 6 .
Fig. 6.Generalized steady-state i L and v SW waveforms through one full switching period of duration T .

Fig. 7 .
Fig. 7. Calculated full-ripple phase durations (left) and operating points (right) both plotted versus load current I OU T .Below 7.5 A the inductor experiences reverse conduction.For I OU T > 24.75 A, capacitor ripple increases to the extent that v SW swings below 0 V inducing unintended reverse conduction in switches.V IN = 48 V, V OU T = 3.3 V, N = 6, f SW = 250 kHz, C 0 = 496 nF, L = 1.125 µH.

Fig. 7 (
left) depicts calculated phase durations plotted versus output load, I OU T , where the time axis is represented as a fraction of total period T .Parameter t 1 is observed to have a strong dependence on load.Fig. 7 (right) plots the value of i L at each instantaneous phase transition giving insight into the inductor's current ripple and dc bias.For V IN = 48 V, V OU T = 3.3 V, N = 6, f SW = 250 kHz, C 0 = 496 nF, and L = 1.125 μH, we see that the lower bound for continuous forward conduction, or boundary conduction mode (BCM), should occur at 7.5 A, below which the inductor current experiences negative current flow unless the clocking scheme is altered to facilitate DCM.

Fig. 8 .
Fig. 8. Theoretical switch node voltage v SW (t) (top), inductor current waveform i L (t) (middle), and phase durations (bottom) for three scenarios: Assuming flying capacitor ripple only (green), inductor ripple only (red), and both capacitor and inductor ripple (blue), the latter being the analysis presented in this work.Phase 1A sees up to 19% timing error when capacitor ripple is neglected, while Phase 1B can have up to 75% timing error when inductor ripple is assumed negligible.V IN = 48 V, V OU T = 3.3 V, I OU T = 14.5 A, N = 6, f SW = 160 kHz, C 0 = 496 nF, L = 1.125 µH.

Fig. 9 .
Fig. 9. Photograph of the constructed SDIH prototype with a capacitor network order of N = 6.Due to the proposed topologies symmetry, the reverse side is largely identical with inverse component naming on flying capacitors and switches.A best-fit cuboid encompassing all components measures 25.8 mm × 31 mm × 3.6 mm, where the converter's overall height is limited by through-plane inductors L 1 and L 2 .

Fig. 11 .
Fig. 11.Volume breakdown of the hardware prototype.Overall converter volume breakdown (left) and component volume breakdown (right).

Fig. 13 .
Fig. 13.Measured i L and v SW waveforms that validate the calculated large ripple operating points depicted in Fig. 7.A minimum load of I OU T = 7.5 A demonstrates BCM (top), and a maximum load of I OU T = 24.75A results in v SW reaching 0 V (bottom).V IN = 48 V, V OU T = 3.3 V, N = 6, f SW = 250 kHz, C 0 = 496 nF, L = 1.125 µH.

Fig. 15 .
Fig. 15.Measured efficiency curves for a discrete hardware prototype demonstrating the proposed SDIH converter topology and operating using the derived full ripple split-phase control scheme.V IN = 48 V, N = 6, f SW = 750 kHz, C 0 = 496 nF, L = 150 nH.

TABLE I COMPONENT
COUNT COMPARISON

TABLE II COMPONENT
DETAILS FOR DISCRETE HARDWARE PROTOTYPE