An on-chip W-band bowtie slot antenna in silicon

This paper presents a W-band fully on-chip bowtie slot antenna over a grounded low resistivity silicon substrate fabricated in 180 nm BiCMOS process. The measured results show that the proposed antenna could provide a wide input bandwidth covering the whole W-band. The simulated gain at 90 GHz is -1 dBi when considering several realistic effects.


INTRODUCTION
(Bi)CMOS processes have recently been proven to be a viable platform for millimeter wave (mm-wave) transceivers [1]. To achieve a highly integrated system and to address the complex problem of delivering/accessing an mm-wave signal off the chip, a high performance antenna is required. As a potential solution to be this challenge, integration of silicon based transceivers with on-chip antennas (OCAs) have been proposed, using a variety of techniques [2][3][4][5][6][7]. With the help of off-chip components, including a superstrate [4] and lens [2,3], high gain and high efficiency antennas have been achieved. However, additional processes are required during/after fabrication to implement these off-chip antennas, and thereby increase the cost of the whole system.
In this paper, a fully on-chip bowtie shape slot antenna is proposed. The antenna is fabricated in 180 nm BiCMOS process with 275 µm thick SiGe substrate with a conductivity of 12.5 S/m. The measured antenna -10 dB input reflection coefficient covers the whole W-band (70~110 GHz) and agrees well with the full-wave simulation using HFSS. The simulated gain is around -1 dBi.
II. PROPOSED ON-CHIP BOWTIE SLOT ANTENNA Figure 1 shows the micrograph of the proposed bowtie slot antenna. The antenna is placed on the top metal layer (M6) and occupies an area of 1.4 mm × 0.9 mm (0.44 λ 0 × 0.28 λ 0 ). The ground plane of the antenna is located below the SiGe substrate. A 50 Ω coplanar waveguide (CPW) line is employed to feed the slot antenna and connected with a 50 Ω matched onchip bond pad [8]. The corners of the bowtie are optimized to provide better detour for current flowing around the slot edges, thereby improving the antenna bandwidth. Due to the metal density limit rules imposed by the foundry, array of 5 µm × 5 µm dummy holes are placed all over the antenna on M6 as illustrated in Fig.1. Simulation results prove that the effect of holes could be ignored since the hole size is much smaller than the effective wavelength of the substrate.

A. Input Reflection Coefficient
The antenna input reflection coefficient is measured while probing the antenna with a W-band RF-probe. A short-openload calibration of the probe was conducted before the measurement. Fig.2 shows the comparison between the measured and simulated antenna input reflection results. As expected from the simulation, the proposed bowtie slot antenna shows a very wide -10 dB input bandwidth covering the entire W-band. Such wide input bandwidth is also contributed by the significant loss inside the antenna substrate and thereby a reduction in antenna quality factor. To validate the measurement, the same test was repeated on several chip samples and the results are very similar compared to each other. As shown in Fig.2, there is a slight difference between the simulation and measurement above 90 GHz, which could be due to the measurement interference or a tiny mismatch in the bond pad.

B. Broadside Gain
The bowtie slot antenna is fabricated in the corner area of a 5 mm × 5mm chip die as shown in the inset of Fig.3. Because the antenna is sharing the same substrate with other circuitry, the antenna radiation performance will be affected by waves travelling inside the SiGe substrate, as well as the total substrate size and the existence of metallic parts above the substrate used for circuitry. Also, since a silver adhesive tape is  used to attach the chip die to the chuck of probe station, simulations have been conducted to show how this affects radiation compared to the case with a PEC ground under the SiGe substrate. To do that, the conductivity value of 10 5 S/m is assumed for the silver adhesive used.
In Fig.3, the simulated broadside gain versus frequency of the proposed antenna is shown for three cases, namely (i) simulation of 1.4 mm × 0.9 mm antenna with a PEC ground; (ii) simulation of 1.4 mm× 0.9 mm antenna with a silver adhesive ground; and (iii) simulation of 5 mm× 5 mm total chip area. As shown in Fig.3, it is observed that considering the lossy ground made by the silver adhesive (instead of a PEC) slightly affects the gain. More importantly, including a total 5 mm chip area in the simulation significantly affects the antenna radiation performance. It also implies that without the use of an effective shielding to prevent the wave from travelling inside the SiGe, the same antenna located on different locations of the chip may provide rather different radiation performance.
In the measurement, the antenna gain calibration is based on two off-the-shelf horn antennas separated by the same distance as that between the horn and the on-chip antenna. Insertion losses in the probes and additional 0.5 dB transition loss between the probe and on-chip CPW were considered in the gain calculation.
Several constraints limit the accuracy of the OCA underprobe measurement. One of the difficulties is that, without the assistance of through-substrate-via (TSV) technology or offchip design, the antenna feeding probe has to be in the proximity of the near-field range of the antenna under test. The interference between the bowtie antenna and probe will degrade the results in two ways: (i) the RF probe itself is acting as an antenna such that it receives/transmits power directly from/to the horn antenna, though in our case this was very moderate; (ii) the wave incident on the probe could be reflected back to the OCA, and vice versa, causing interferences. It was observed during our measurement that careful placement of absorbers, to some extent, will alleviate the problem. At 94 GHz, the measured (averaged) 1dB gain is considered as an approximate value.