A General Analysis of Resonant Switched-Capacitor Converters Using Peak Energy Storage and Switch Stress Including Ripple

This article presents a general analytical framework enabling the large-signal characterization of resonant switched-capacitor (ReSC) power converters that accounts for passive component voltage and current ripple, for operation at and above resonance. From this, appropriate phase durations for minimized rms currents are derived, in addition to expressions for total passive component volume using an intuitive peak energy method. An example hardware prototype validates both the derived waveforms and timings—as well as total passive volume—through three comparable hardware configurations, one of which minimizes passive component volume. In addition, the proposed technique formulates analytical expressions for both rms currents and peak blocking voltages, facilitating refined loss estimation and component selection. Subsequent calculation of the large-signal volt-amp switch stress metric allows a more accurately quantified tradeoff between active and passive components compared to prior work, which has not fully accounted for ripple. Four common ReSC topologies are exemplified throughout, with topology-specific parameters documented for reference.


I. INTRODUCTION
R ESONANT switched-capacitor (ReSC) power converters (see Fig. 1) are a relatively new class of converter topology primarily relying on capacitors as energy transfer elements, leveraging their superior energy density over magnetics [1].However, to mitigate the well-known slow-switching limit (SSL) impedance [2] and associated pulse inrush currents in pure switched-capacitor (SC) converters, some small inductance is introduced to enable "soft-charging" of the flying capacitors [3] The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (email: nathanmilesellis@berkeley.edu; nathanbrooks@berkeley.edu;blackwell @berkeley.edu;rose_abramson@berkeley.edu; scoday@berkeley.edu;pilawa@berkeley.edu).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TPEL.2023.3285745.
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ReSC converter volume as compared with more traditional architectures (e.g., buck/boost).
Prior literature has presented analytical methods to calculate both the minimum achievable passive component volume and output impedance for these types of converter; however, these analyses are often limited to ReSC converters operating exactly at resonance (see, e.g., [12] and [13]).While this operating point facilitates zero-current switching (ZCS) for reduced switching loss, other work in [14], [15], [16], [17], [18], [19], [20], and [21] has established that operating some ReSC converters above resonance can significantly improve overall converter efficiency through a reduction in rms currents and associated conduction losses, despite increases in relative switching loss.Although above resonance operation has been demonstrated in practice, a characteristic analysis has been lacking.The framework presented in [12] is not applicable, while a provision (parameter β) in [13] and [22] characterizing the ratio of rms to dc current allows the analysis therein to be extended to above-resonance operation without being explicitly derived.
This article, therefore, contributes a generalized analytical technique enabling the complete characterization of ReSC operation while operating both at and above resonance.No smallripple approximations are made, resulting in an accurate largesignal solution accounting for both voltage and current ripple on capacitors and inductors, respectively.In addition, the presented analysis is simplified with respect to [12] (which required instantaneous power integrals to be evaluated) and only requires the use of inherent topology characteristics, such as the number of components and phases, and standard charge flow vectors, similar to those described by the analytical method for pure SC converters presented in [2].
While the methodology presented here can be extended and applied to any ReSC converter topology, this article restricts its application to a subset of ReSC converters capable of operating effectively above resonance.Specifically, this article considers fixed-ratio (N :1) ReSC converter topologies with a single inductor placed in series with the low-side port, as is the case for several common example topologies depicted in Fig. 1.Termed "direct" in [22] and [23], "inductor-at-the-output" in [19], and here as "inductor-at-the-low-side-port" (to accommodate step-up 1:N variants), these structures are capable of operating both at and significantly above their nominal resonant switching frequency.When operated above resonance, the inductor enters a forward continuous conduction mode (CCM) where the converter exhibits a lower sensitivity to component or timing mismatch, in addition to the aforementioned reduction in rms current.
In contrast, LC-tank-type ReSC structures (see, e.g., [10], [24], [25], [26], [27], and [28]), termed "indirect" in [23], are constrained to at-or near-resonant operation since they incur either excessive circulating currents when operated above resonance or hard-charging losses when operated below resonance without the introduction of discontinuous conduction states or dynamic off-time modulation (DOTM) [27], [29], [30].Consequently, tank-based topologies have a susceptibility to component and timing mismatch and require either active autotuning control [31], [32] or accurate component tolerance and stability with aging, temperature, and bias-disqualifying Class II multilayer ceramic capacitors (MLCCs) [33] and softsaturating magnetics.Conversely, the switches within tank topologies generally experience favorable constant blocking voltages that are independent of load since voltage ripple is hidden within LC-tank elements [17], [28]-serving to simplify design.Both "direct" and "indirect" topology variations exhibit theoretically identical total passive component volume when operated at resonance, irrespective of inductor count, when inductance is distributed accordingly [12].However, unless a common core can be used in indirect multi-inductor designs, the magnetics of direct single-inductor ReSC designs scale more favorably [34], lending further preference to direct variants.Moreover, the LC tanks within indirect topologies require bidirectional inductor current, necessitating a 2× increase in flux density ripple, ΔB, as compared to the unipolar current observed in equivalent direct converters, where much of the spectral power is concentrated at dc, having implications for magnetic losses [35], [36].
Following this reasoning, the subset of ReSC converters evaluated in this article (single-inductor "direct" topologies) is simultaneously highly attractive and challenging to fully analyze.Analytical expressions for peak ratings are derived for both the capacitor voltages and inductor current, aiding the practicing engineer in component selection.These expressions also permit a derivation of the minimum passive component volume, both at and arbitrarily above resonance.The general expressions derived herein collapse into the results presented in [12] when constrained to resonant operation, further validating this general approach.In addition, this framework is used to improve the fidelity of calculated switch stress metrics.Prior switch stress computations typically use simplified voltage and current calculations to characterize the switches, such as neglecting the effects of capacitor voltage ripple on switch voltage [2], [12], [20], [37] or neglecting the effects of inductor current ripple on switch current [2], [12].Here, we calculate the precise peak switch voltages and rms currents and demonstrate that prior simplifying assumptions can lead to significant undersizing of switches for high-ripple designs.Moreover, while minimized passive component volume is emphasized, the presented framework assists with global optimization efforts (see, e.g., [38]) by providing the large-signal values and waveforms needed for accurate loss estimation.
Table I summarizes, categorizes, and highlights the limitations of several analytical approaches to SC and ReSC analysis presented in the literature.For example, when assessing passive volume, Ye et al. [12] address both capacitor voltage ripple, Δv C , and inductor current ripple, Δi L , for both direct and indirect topologies, strictly at resonance.However, the impact of ripple on switch stress is not considered.
The rest of this article is organized as follows.Section II presents the base assumptions and analytical framework necessary to characterize the operation of a general (lossless) fixedratio ReSC topology.Section III introduces closed-form expressions for phase timings both at and arbitrarily above resonance.A direct energy-based approach for quantifying total passive component volume/mass through assessment of per-component peak energy storage requirements is proposed in Section IV, along with an optimization method to minimize total passive volume.Generalized results are presented for several common ReSC topologies.Section V presents a hardware example illustrating the described analysis.Switch stress including full capacitor voltage and inductor current ripples is assessed in Section VI.Section VII summarizes and discusses the results obtained in Sections III-VI and contextualizes the tradeoffs between different ReSC topologies.Finally, Section VIII concludes this article.

II. FRAMEWORK DEFINITION
The proposed framework stems from conventional vectorized descriptions of SC converters in [2], [5], [22], and [58] and is derived from fundamental charge-balance and zero volt-second principles.In addition, we assume periodic steady-state operation, with dynamic response beyond the scope of this article.Ideal circuit elements are also assumed, with no ohmic losses or parasitic effects.This assumption is valid for moderate-to heavy-load operation and where ohmic losses have minimal impact on the large-signal dynamics of a converter designed for high efficiency (e.g., η ≥ 95%).Phase durations are chosen, so each phase begins and ends with the same inductor current, implying zero inductor volt-seconds within each phase.This constraint is justified in Appendix A and validated with hardware in Section V. Finally, input and output bypass capacitance is assumed large with respect to the flying capacitors; thus, the input and output sources can be considered ideal as is done in many existing models and analyses [2], [5], [9], [17], [22], [56].Finite input/output bypass capacitors may be included as part of a comprehensive analysis that facilitates port voltage ripple constraints [59], [60]; however, this adds significant analytical complexity and is omitted here for conciseness.This framework applies not only to two-phase ReSC, but also to multiphase/multiresonant converters-more than two phases in a switching period-such as the flying capacitor multilevel (FCML) converter in Fig. 1

(b).
To begin, several topologically defining vectors are obtained through careful analysis and deduction for each ReSC structure under consideration.These are summarized in Table II and listed in order of appearance throughout the following sections.General matrices are defined in addition to example values for the series-parallel topology depicted in Fig. 1(a).

A. Charge Flow Matrices: a X
As is typical for purely capacitor-based converters [2], periodic steady-state analysis of ReSC structures also begins by assessing charge flow through the converter.To do so, charge flow quantities through all the circuit elements are normalized to the amount of charge periodically conducted by the high-side port, q HI , as q X,ji = q HI a X,ji (1) where X is the circuit element type (e.g., capacitor, C; inductor, L; or switch, S), j is the phase index, and i is the element index.The charge quantity q HI is itself an operating parameter defined as Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.where I HI is the average high-side port current and f SW is the periodic switching frequency (with associated switching period T SW ).Subsequently, the normalized charge flow matrix, a X , is comprised of topologically dependent entries, which are invariant of operating point (i.e., power level, voltage, and switching frequency), whereas q HI scales the charge conducted through all the elements in unison, while preserving their relative relationships.Periodic steady-state requires the capacitors conduct zero net charge per full switching period, as described by where N P is the number of operating phases.Utilizing this characteristic, values for a C , and subsequently a L and a S , can then be obtained by inspection.For example, Fig. 2 depicts the periodic steady-state charge flow through an N :1 series-parallel step-down converter operating with two switching phases (N P = 2) and with N C = N − 1 flying capacitors.During phase 1, charge q HI is provided by the high-side source V HI and is admitted by all the series-connected flying capacitors.In adherence with (3), each flying capacitor must then release charge q HI during phase 2. Subsequently, the normalized capacitor charge values, a C,ji , for the series-parallel topology are where the first row's entries correspond to phase 1 and the second row's entries correspond to phase 2. The charge matrices a L and a S are similarly determined.
Also apparent from Fig. 2, the charge admitted by V LO over both phases is equal to q LO = (N C + 1) q HI , yielding the converter's voltage conversion ratio Moreover, converter power throughput, P HI , may be expressed in terms of the average high-side charge q HI as Table VIII records the charge flow matrices for the flying capacitors, a C , the low-side inductor, a L , and the switches, a S , for the four common ReSC topologies depicted in Fig. 1.

B. Mid-Range Flying Capacitor Voltage Vector: v
Each flying capacitor's mid-range voltage is defined as the dc value symmetrically centered between the maximum and minimum voltage, as dictated by ripple.This value is distinct from the time-averaged dc voltage, which can deviate significantly in multiphase converters.Here, the mid-range voltages can be derived from an assumption of zero average voltage across the inductor (i.e., zero volt-seconds) within each phase.Under this assumption, the inductor may be treated as a short circuit when applying average Kirchhoff's voltage law (KVL) loops to each phase.Subsequently, the absolute mid-range voltages of each flying capacitor, V C i , may be expressed with respect to the high-side voltage, V HI , as where v i represents the normalized (to V HI ) mid-range voltage.By applying per-phase average KVL to the N :1 series-parallel depicted in Fig. 2, during phase 2, each flying capacitor is connected in parallel with-and thus holds a voltage equal to-V LO .

C. Capacitance Vector c
While some topologies have no strict constraints on capacitance sizing (e.g., FCML converter), others require specific relative sizing to prevent hard-charging and retain simplified clocking schemes, as derived in [5], [58], [65], and [66] for example.The absolute capacitance of each flying capacitor, C i , is normalized to a single capacitance value, C 0 , as and by doing so, the required relative capacitor relationships are preserved as the single value C 0 changes-a useful feature Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
for the analytical passive component volume minimization performed in Section IV.
Considering the exemplar series-parallel topology, all the capacitors conduct equal charge in each phase and must express identical voltage ripple characteristics when connected in parallel during phase 2. Thus, by Q = CV (and to ensure soft-charging behavior), each capacitor must be equal in value, yielding The normalized capacitance vector, c, is documented in Table VIII for the series-parallel, Dickson, and Fibonacci topologies; for the FCML topology, all the capacitances are chosen to be equal for simplicity.

D. Lumped Equivalent Capacitance Vector κ
During each switching phase j, the inductor forms a secondorder resonant impedance network with the connected flying capacitors, which have an equivalent lumped capacitance, C e,j .This value is then normalized with respect to C 0 , yielding κ: In phase 1 of the example series-parallel converter (see Fig. 2), all the capacitors are connected in series and the equivalent capacitance seen by the inductor is whereas in phase 2, all the capacitors are connected in parallel relative to the inductor and the equivalent capacitance is More generally, the normalized equivalent capacitance vector, κ, is defined and shown for the series-parallel topology as and is tabulated for additional topologies in Table VIII.This section has obtained fundamental topology-dependent parameters.However, in order to fully characterize the largesignal behavior of an ReSC converter, including passive volume and switch stress both at and above resonance (discussed in Sections IV-VII), switching-frequency dependencies must also be derived.Section III explores how phase timings and current waveforms depend on switching frequency.

III. PHASE TIMINGS
A "direct" ReSC converter can be switched at its natural resonant switching frequency, f sw,0 , to achieve ZCS at each phase transition.However, dissimilar to "indirect" or LC-tank topologies, the switching frequency of a direct topology may also be increased without incurring increased circulating currents [16].Subsequently, we define a free parameter, Γ, as the ratio of the actual switching frequency, f sw , to the natural resonant switching frequency Resonant ZCS is obtainable at Γ = 1 (i.e., at-resonance operation), while for Γ > 1 (i.e., above-resonance operation), the inductor enters CCM.In practice, values of Γ < 1 (i.e., below-resonance operation) would only be implemented with a modified discontinuous conduction mode or DOTM [29], [30]; otherwise, SSL losses would reemerge.
The motivation for operation above resonance operation has been explored in [14], [15], [16], [17], [18], [20], and [21] as a method for reducing conduction losses and improving overall efficiency.However, for several topologies-including the FCML converter and resonant N -phase implementations of Cockcroft-Walton and Dickson converters [67], [68]-the phase durations depend heavily on the relationship between the natural resonant switching frequency and the implemented f sw .Given that a rigorous proof of the necessary phase timings for above resonance operation has not been demonstrated in the literature, Rentmeister et al. [16], [17] instead relied on closed-loop control to converge on appropriate phase durations.
Therefore, this section expands on an earlier version of this work in [21] to explicitly derive the required relative phase durations for any given switching frequency at or above resonance (Γ ≥ 1).Continuous closed-form expressions are derived for phase-timing durations, which minimize the peak, peak-to-peak, and rms inductor current both at resonance and for arbitrary frequencies above resonance.The presented analysis yields a robust method for explicitly determining the phase durations as well as the inductor current waveform used for the switch stress analysis in Section VI.

A. Phase Duration Vector τ
Each phase duration, t j , can be defined in terms of the full switching period, T sw , using a normalization parameter τ j t j = T sw τ j (16) where T sw defines the sum of all N P phase durations The normalized phase duration vector, τ , is deduced from the resonance of the inductor current i L (t) for each topology and as a function of Γ.
When operating at the resonant switching frequency, f sw,0 (i.e., Γ = 1), each phase is half-wave resonant with i L (t) starting and ending at 0 A. Thus, the phase duration, t j , equals half the duration of the natural resonant period, T 0,j , of the lumped LC resonant tank in the jth phase or as per (16).
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Fig. 3. Two adjacent phases of the inductor current waveform, i L (t), operating above resonance.Each phase constitutes a symmetrically centered sinusoidal segment with angular frequency governed by (19).
The natural angular frequency, ω 0,j , associated with T 0,j can be expressed as since parameter κ j defines the lumped equivalent capacitance.
Calculating the phase durations, t j , for operation above resonance (i.e., Γ > 1) requires further analysis.Within each phase j, if the inductor is subjected to zero volt-seconds, then it forms a symmetrically centered sinusoidal segment,1 as depicted in Fig. 3. Continuity in i L (t) between adjacent phases (including j = N P and j = 1) can be expressed mathematically as where I pk,j is the peak current in phase j.Furthermore, during phase j, the inductor conducts charge q L,j , where which relates to the known normalized charge flow matrix, a L , and can be rearranged with respect to I pk,j as Combining the phase-to-phase current continuity (20) and perphase charge flow ( 22) yields a L,j ω 0,j tan ω 0,j tan ω 0,j+1 Equation ( 23) can be solved using ( 19) and ( 16), to determine appropriate normalized phase durations, τ j , for each phase.The resultant vector, τ , is documented for the four topologies in Table VIII.For all the two-phase converters, τ j is notably independent of Γ, as will be demonstrated for the series-parallel converter in Example 1.However, as detailed in [21], phase durations for the FCML converter vary with Γ.This derivation, documented as Example 2, is more complex, yielding an implicit transcendental equation with an approximated numerical solution.

B. Example 1 (Series-parallel converter):
Consider the twophase series-parallel topology with arbitrary conversion ratio N in Fig. 2 as an example.Substituting the normalized equivalent capacitance vector, κ j , (from Table VIII) into the natural angular frequency, ω 0,j , during each phase in (19) yields and with the corresponding relationship between these two frequencies as Next, (26) and values for normalized inductor charge flow, a L,j (recorded in Table VIII) are substituted into the steady-state charge flow and inductor continuity constraint given by (23), yielding The argument of each tangent is then equated to find a relationship between the two phase time durations For this two-phase topology, we have and therefore the normalized phase durations, τ j , become where τ only varies with conversion ratio and not Γ.This result is also recorded in Table VIII.
In addition, substituting ( 26) and ( 28) into (20) reveals I pk,1 = I pk,2 -a consistent result for all two-phase converters considered in this article.
C. Example 2 (FCML converter): While Example 1 exhibits consistent phase durations at and above resonance, the phase durations are more complex for the higher order (N ≥ 3) resonant FCML converter.Extensive literature explores the dynamic behavior of the pulsewidth modulation (PWM) regulating FCML converter, both using time domain [47], [48], [50], [52], [53], [69] and frequency domain [70], [71], [72] methods.However, less discussion surrounds the resonant fixed-ratio variation capable of achieving smaller magnetic volume.In regulating mode, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.conventional symmetric phase-shifted PWM dictates identical phase durations.However, in resonant mode, phase durations deviate to accommodate the differing natural resonant frequencies within each phase.This adjustment improves capacitor balancing and overall converter efficiency [16], [17], [21].While works [16] and [17] explored above-resonance operation of N = 3 and N = 6 FCML converters, these works expanded on the valley current control scheme in [73] to converge on optimal phase durations through active feedback without providing an analytical solution.Here, we provide an accurate closed-form solution for appropriate phase timings, accounting for all Γ ≥ 1.
Fig. 4 depicts the phase progression for an exemplar FCML converter with N = 5.Using this same nomenclature, (31) describes the normalized lumped capacitance presented to the inductor during each phase, κ, in terms of arbitrary integer conversion ratio N Consequently, the first and last phases have identical durations, while all phases in between have a different (but equal) duration.Thereby, we can limit consideration to the first and second phase intervals only, where the full switching period may be expressed as Evaluating ( 19) with ( 31) and substituting into (23) produces an implicit equation for This implicit equation of phase durations does not reduce analytically, but it can be solved numerically using (32) as a constraint.From inspection of the numerical solution, an accurate closedform expression for the relative phase durations is approximated as a function of N and Γ as Fig. 5 shows both the numerical and analytical approximations for τ 1 and τ 2 for an N = 5 FCML converter example.The error between the numerical and analytical results is negligible, validating the accuracy of ( 35) and (36).Finally, Fig. 6 depicts simulated inductor current waveforms for various Γ, highlighting the change required in t 1 (and correspondingly t 2 ) to ensure zero volt-second per phase.

IV. PASSIVE COMPONENT VOLUME/MASS
To characterize passive component volume/mass and subsequently enable converter size/weight minimization, expressions are derived for both total flying capacitor and inductor volume/mass, as dictated by their peak energy storage requirements.
A direct energy method is demonstrated here, expanding on the flying capacitor analysis in [58], and using the phase timings derived in Section III to further obtain expressions for peak inductor energy.Dissimilar to [12], this approach circumvents the need to analytically generalize and integrate instantaneous power waveforms (i.e., p(t) = v(t) • i(t)) for every passive component.
While the results of the proposed method and [12] are equivalent for operation at resonance, the proposed method generalizes the passive component requirements for arbitrary switching frequencies above resonance (i.e., Γ > 1) where both the peak flying capacitor voltage and inductor current are diminished.

A. Total Peak Flying Capacitor Energy Storage
To calculate the total flying capacitor energy storage requirement, consider the peak voltage expressed on each flying capacitor, as a function of load, while noting that these events may not occur simultaneously in time for each flying capacitor.Moreover, since a flying capacitor may admit charge over multiple phases before achieving its peak voltage-as is the case for the multiresonant doubler [61] and cascaded series-parallel [62] topologies-a modified charge flow quantity âC,i is defined describing the maximum deviation in stored charge on the ith flying capacitor throughout a full switching cycle. 2 For converters in which each flying capacitor only admits charge during a single phase (e.g., Fig. 1), âC,i is defined as which, for two-phase converters, may be simplified to since each capacitor must admit and release the same quantity of charge across both phases in periodic steady state.Subsequently, the peak-to-peak voltage ripple, Δv pp,i , on each flying capacitor, i, may be described as The peak energy storage requirement follows for the ith capacitor across all phases as where the peak capacitor voltage is the mid-range voltage plus half the peak-to-peak voltage ripple, or Δv pp,i .The total peak flying capacitor energy over all N C capacitors is then Substituting ( 6), (39), and ( 40) into ( 41) yields where This result is similar to that described in [58], where notations α, β, and θ are used in place of A 1 , A 2 , and A 3 .Furthermore, the impact of switching frequency on capacitor ripple, and therefore peak storage, is subsumed within q HI , recalling (2) and (15).The total volume of the capacitive elements can then be computed as where ρ C is the volumetric energy density (J/m 3 ) of the chosen capacitor technology.Alternatively, total mass (kg) may be defined using each components' specific density [1].Similarly, a cost density metric defining stored Joules per unit cost (J/$) may be used.

B. Peak Inductor Energy Storage
Next, peak inductor energy storage is calculated, accounting for converter operation above resonance (i.e., Γ > 1).For simplicity, the inductor is assumed to have a constant inductance with applied current bias and to be saturation limited, as is often the case for low-loss ferrite materials.Consequently, the minimum inductor volume is proportional to the peak energy stored therein.
First, the per-phase resonance equation ( 19) is rearranged to give and ( 15), ( 16), (18), and ( 19) are substituted into the peak inductor current in (22) I pk,j = q HI a L,j ω 0,j 2 sin ω 0,j Using ( 47) and ( 48), the peak inductor energy over all phases, j, can then be expressed as where For converters with τ j independent of Γ, B 1 is simplified since τ j = τ j | Γ=1 .Furthermore, for all the converters operating in resonant ZCS mode (i.e., Γ = 1), (50) reduces to The total inductor volume can then be computed as where ρ L is the volumetric energy density (J/m 3 ) of the inductor.Again, specific density (J/kg) or cost density (J/$) may alternatively be used in mass-or cost-constrained applications, respectively.

C. Minimization of Passive Components
Passive components typically comprise the large majority of a converter's volume (or mass).Thus, a converter's volume may be approximately minimized by considering only the volume of the passive components.To do so, an expression for total passive volume-as defined by peak energy storage requirements-is constructed using ( 46) and ( 52) Total passive volume is then minimized by differentiating with respect to the normalized capacitance C 0 ) which is solved explicitly for the minimizing normalized capacitance C * 0 as for a given Γ, V HI , q HI , and passive energy density ratio ρ C /ρ L .The composite terms A 1 , A 3 , and B 1 are all known functions of topology and a given choice of switching frequency (i.e., Γ).By then substituting C * 0 into (47), we obtain the corresponding inductance value, L * , that maintains f sw,0 while minimizing passive volume.
Back substituting ( 55) into ( 53) and replacing q HI using (2) yields the minimal achievable total passive component volume Furthermore, ( 56) can be normalized with respect to power throughput, natural resonant switching frequency f sw,0 [as per (15)], and capacitor energy density ρ C .The resulting normalized minimum total passive component volume, M * vol , may be used to directly compare different topologies and is solely a function of the above-resonance parameter, Γ; the ratio of passive densities, ρ C /ρ L ; and invariant topological parameters: (57) This is a similar normalized passive volume metric as obtained in [12], but now includes terms accounting for above resonance operation.The normalized minimum passive volume is visualized across a range of conversion ratios, N , in Fig. 7 for the Dickson (odd), Fibonacci, FCML, and series-parallel topologies depicted in Fig. 1.The relative energy density ratio of capacitors to inductors in this plot is chosen as ρ C /ρ L = 100, following the empirical scaling trends analyzed in [1].As the switching frequency is increased above resonance, the minimum passive volume also decreases due to a reduction in peak voltage and current ripple.However, as Γ is increased further, the reduction in minimum passive volume becomes relatively small as ripple becomes negligible relative to dc values.
One additional consideration not captured in the preceding analysis is capacitor-ripple-induced clamping-operation where capacitor voltage ripple imposes a reverse voltage bias on inactive switches.This condition leads to reverse conduction in practice, resulting in unintended converter operation and significant losses.Detailed in [58] for the Dickson topology, here, we record similar power limitations for the three remaining topologies in Table III.These limits are obtained by setting the flying capacitor voltage ripple-as related to load via (2) and

TABLE III MAXIMUM POWER (VOLTAGE RIPPLE CONSTRAINED)
(39)-equal to the maximum allowable ripple condition, i.e., the point at which unintended reverse conduction begins to occur.As expected, this constraint scales with input voltage, switching frequency, and C 0 .Therefore, it could be beneficial to design with volume suboptimal C 0 > C * 0 , so as to extend the load range in lower voltage applications subject to strict switching frequency constraints.

V. HARDWARE VALIDATION
The preceding analysis is applied to the design of a 5:1 (i.e., N = 5) FCML converter hardware prototype, whose schematic is depicted in Fig. 1(b).The printed circuit board, switches, and gate driving circuitry-depicted in Fig. 8 and listed in Table IV-are identical to the hardware demonstration in [21], while the passive components are replaced with values minimizing total passive volume.Switch operation is controlled in accordance with the clocking scheme depicted in Fig. 4. Table V defines this design example's chosen operating point.The target output power of P HI = V HI • I HI = 77 W corresponds to the demonstrated peak efficiency point in [21] when using the same switching devices at the same input voltage of V HI = 200 V.  Similarly, Γ = 1.25 was selected, having demonstrated a good balance between switching and conduction losses in [21].To emphasize achievable passive volume reductions, a modestly high switching frequency of f sw = 250 kHz is chosen here, implying f sw,0 = f sw /Γ = 200 kHz.
We note that the choice of Γ, f sw , and the selected switch sizings largely dictate converter efficiency.Section VI presents a method to derive both peak blocking voltage, V ds,max , and rms current, I rms , for each switch as a function of Γ, which facilitates conventional loss estimation and optimization across frequency, with the effects of large ripple behavior now fully modeled.However, a detailed loss assessment is beyond the scope of this article, with the following design example focusing on passive component volume only.In practice, the described design flow may be iterated in conjunction with complimentary large ripple enhanced loss calculations, allowing for comprehensive converter optimization that accurately captures the well-known tradeoff between passive component volume and converter efficiency.
Having specified an operating point in Table V, passive component volume is now calculated in accordance with Section IV.First, the high-side average charge q HI = 1.54 µCas per ( 2) and ( 6)-and the relative phase durations are evaluated as τ 1 = 0.233 and τ 2 = 0.178 using ( 35) and (36) To demonstrate that C 0 = C * 0 results in minimized total passive component volume, three sets of passive componentsdepicted as Cases 1-3 in Fig. 9-were implemented in hardware.To ensure consistent energy densities ρ C and ρ L across all the instances of the same passive type, regardless of value or applied bias, each passive component is constructed using series and/or parallel combinations of either a small unit capacitor or unit inductor.These unit elements, summarized in Table VI, both have competitive energy densities representative of their respective technologies [1].A Class I MLCC capacitor (e.g., C0G/NP0) with ρ C = 8800 J/m 3 is used, given the stability, low loss, and achievable tolerances of these dielectrics in tuned ReSC designs [10].Likewise, the unit inductance is a low-loss stable  ferrite with ρ L = 123 J/m 3 .Using these densities, the prescribed operating parameters, and (55), the normalizing capacitance value minimizing total passive component volume is found to be C * 0 = 44 nF, with associated inductance L * = 3.4 µH using (47).Finally, having obtained C * 0 , Table III is consulted to ensure that the target power of 77 W does not exceed the capacitor ripple limitation.In this case, P MAX = 88 W ensuring correct operation with a 10% margin.
For each of the three cases in Fig. 9, values for both C 0 and L differ, but all the cases express an identical natural resonant frequency, f sw,0 , leading to the same switching frequency, f sw , for a given Γ.Case 1 uses a capacitance C 0 twice as large as the minimizing value (i.e., C 0 > C * 0 ), Case 2 uses the optimal design choice (i.e., C 0 = C * 0 ), and Case 3 uses a capacitance C 0 half the minimizing value (i.e., C 0 < C * 0 ).Fig. 10 compares the resulting total passive volumes with the theoretically calculated volume using (53).The theoretical volume assumes that all passives are rated at their precise maximum energy storage requirement, with no voltage or current derating, and a continuum of part availability.Conversely, the chosen unit inductor has a practical current derating of 2.9 A (instead of 3.3 A) to avoid saturation and ensure a stable inductance value.Similarly, while the flying capacitors nominally experience dc voltages in multiples of 40 V, a 50-V dielectric is chosen to accommodate each element's voltage ripple.Similar approximations are expected for practical  4 with phase timing durations calculated using (35) and (36).For each phase, the inductor current waveform is a centered symmetric sinusoidal segment, further validating the zero volt-seconds per phase assumption.
design constraints and, as demonstrated in Fig. 10, lead to a realized passive volume inflated from the theoretical.However, the applied deratings do not significantly alter the optimal value of C * 0 and L * , provided that a similar degree of voltage/current margin is applied to both capacitors and inductors.To illustrate this, a 10% derating is applied to each passive's voltage or current, which when squared in ( 40) and ( 49) gives a 21% increase in expected volume.This modified theoretical result is also plotted in Fig. 10, showing closer agreement with volumes measured in practice.56) and plotted in Fig. 10, further validating the preceding analysis.

VI. SWITCH STRESS
Sections IV and V aim to minimize the total passive component volume of capacitors and inductors while assuming that, in practice, these elements comprise the large majority of a converter's overall volume.However, this minimization may incur increased voltage and current ripple, which would subsequently be imposed on the adjacent switching devices.This, in turn, may lead to increased switch stress, resulting in volume/loss increases within the active devices.One conventional metric characterizing switch stress is the volt-amp (VA) product [2], [12], [22], [74].This metric assumes linear device scaling and commonly serves as a proxy for total switching device area and/or loss in a given converter when summed across all switching devices.That is, an improved VA rating translates to a smaller and/or more efficient power converter.In this article, we propose a VA metric that takes into account the full effect of the inductor current and capacitor voltage ripples, improving upon calculations presented in past literature by providing a metric with greatly increased fidelity.

A. Current Stress
Rather than using average current for the total VA rating, as in [2] and [12], here, we calculate the rms current through each switch-for both at-and above-resonance operation-using the inductor current waveform derived in Section III.Utilizing rms current is similar to the analysis performed in [20] and [37] and captures conduction losses, thermal requirements, and the effects of operating frequency on switch current ripple.
The normalized charge flow, a S,ji , through the ith switching device is obtained using the procedure described in Section II-A, and the results for four topologies are recorded in Table VIII where switches adhere to the naming convention depicted in Fig. 1.In phase j, the ratio of the peak current through switch S i relative to the peak inductor current, as defined in (48), is equivalent to the ratio of respective charge flow or For each switch, S i , the total rms current in a switching period is constructed from a squared sum of per-phase rms currents as where ( 16) and ( 19) are substituted for t j and ω 0,j , respectively, and q HI is substituted for the high-side input current, I HI , using (2).A similar analytical expression for the inductor current Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
rms may be derived as Interestingly, both the switch and inductor rms currents are independent of both C 0 and f sw , varying only with Γ and I HI .For all the two-phase converters, the normalized phase durations are invariant to Γ (i.e., τ j = τ j | Γ=1 ) leading to further simplification of ( 59) and (60).In all cases, an increase in Γ results in reduced rms currents, as expected.
The results in ( 59) and ( 60) have been validated using the measured inductor current waveforms presented in Fig. 11, where switch current waveforms can be extracted from i L (t) on a phase-by-phase basis.

B. Voltage Stress
Prior work in [2], [12], [20], and [37] only calculated switch voltage stresses based on the mid-range capacitor voltages, thereby neglecting the effects of capacitor voltage ripple.In this analysis, the peak voltage indicates switch stress and more fairly characterizes the performance of switches under the large ripple conditions typical in converters designed for minimized passive volume.
When a switch is disabled, its blocking voltage, V ds,i , is dictated by proximal flying capacitors.In every phase, large-signal KVL is applied to obtain expressions for the voltage imposed upon each switch, inclusive of flying capacitor voltage ripple.However, the phase and time of occurrence for the peak blocking voltage in each switch is not immediately obvious by inspection.For the ReSC topologies presented in this article, the maximum (or minimum) of V ds in each phase occurs either at its beginning, j start , or end, j end .Therefore, the instantaneous blocking voltage immediately before and after each phase transition must be investigated, after which the maximum value is recognized.
Using the 5:1 FCML converter depicted in Fig. 4 as an example, at the start of phase 1, switch S B5 experiences a blocking voltage of whereas at the end of phase 1, switch S B5 experiences where v 4 is the normalized mid-range voltage of capacitor C 4 and its voltage ripple Δv pp,i is defined by (39).In this case, (61) clearly expresses the peak blocking voltage condition in phase 1. Continuing the analysis for every phase shows that ( 61) is also the maximum switch voltage stress, V ds,max,B 5 , for switch B 5 over the entire switching period.This search is expanded to all the switches, where phases in which a switch is turned ON may be ignored since these switches will have 0 V across them.For convenience, Table VII documents the generalized result for peak voltage stress on each switching element for four common topologies.The calculated peak blocking voltage for the FCML topology is validated against the measured V ds waveforms depicted in Fig. 11 for switches S B,1−5 .

C. Total VA Switch Rating
To compute a converter's total VA rating, the rms current of each switch is multiplied by its corresponding peak voltage, before summing across all the elements: In choosing C 0 to minimize the total passive volume (i.e., C 0 = C * 0 ), ( 55) can be substituted into the V ds,max expressions listed in Table VII.Here, it becomes apparent that V HI can be factored out of all V ds,max expressions.Similarly, the high-side current, I HI , is a factor of I rms , as per (59).Subsequently, the VA rating in (63) can be normalized with respect to input power, P HI = V HI I HI , yielding a metric, M * VA , independent of power level or switching Fig. 12. Normalized switch VA rating versus normalized minimum total passive volume, using ρ C /ρ L = 100.Each curve describes a sweep of 1 ≤ Γ < ∞, where the rightmost point on each curve is Γ = 1.Also plotted is the result when inductor current ripple and/or capacitor voltage ripple are neglected from the switch stress calculations (dashed), as per conventional analysis using small ripple approximations. frequency VA tot V HI I HI (64) and can be used to directly compare the switch utilization of different ReSC topologies.Tradeoffs between this normalized switch stress metric and the normalized minimum passive volume, M * vol , are visualized in Section VII.

VII. DISCUSSION
The previous sections describe a comprehensive large-signal assessment of ReSC converters when operating in periodic steady state, either at or above resonance.Section IV derived a normalized minimum total passive volume metric, M * vol , in (57), while Section VI derived a normalized total switch stress, M * VA , in (64).
These normalized metrics at the minimum volume are evaluated in Fig. 12 for an example N = 5 conversion ratio and ρ C /ρ L = 100-a conservative representation of the peak capabilities of Class I ceramic capacitors (e.g., C0G) and ferrite inductors.Here, each topology can be compared across the full range of possible switching frequencies, from resonant to above resonant operation (1 ≤ Γ < ∞).For a decided Γ, converters with smaller M * vol and M * VA are expected to offer improved performance, with both a reduced minimum passive volume and VA rating.
In Fig. 12, each topology is visibly differentiated when considering its M * vol versus M * VA , indicating a quantitative measure of design tradeoffs.For example, the Dickson topology exhibits the lowest M * VA , suggesting improved efficiency when total switch volume/area is constrained.Viewed differently, for the same conversion efficiency across all four topologies, the Dickson converter's switches are expected to realize a smaller total footprint area/volume.Conversely, the Dickson requires a greater total passive volume than the other topologies when operated at the same power level.The series-parallel topology exists on the opposite extreme: trading worsened total switch stress for superior total passive volume.The FCML and Fibonacci converters lie between these two extremes.For all the converters, both VA rating and passive volume decrease with increasing Γ, due to reduced inductor current and capacitor voltage ripple.However, while the VA rating provides a correlative proxy for the relative switching losses between a set of converter topologies at a given switching frequency, it does not include a frequency-dependent term, and thus, increasing Γ does not directly translate to both a smaller and more efficient converter design.Instead, the VA rating in Fig. 12 should be viewed as informing the relative loss dissipation between topologies at a specified switching frequency, where total loss estimates are calculated separately.The choice of a specific switching frequency is dictated by conventional loss calculations (see, e.g., [13] and [22]), which can now be augmented with the rms of complete current waveforms and ripple enhanced blocking voltages, as derived in Section VI.
To further emphasize the improved fidelity of the presented analysis, Fig. 12 also depicts the resulting curves if either capacitor voltage ripple, inductor current ripple, or both are neglected in the calculation of M * VA .In the "no ripple" case, the switch voltage is calculated using the mid-range capacitor voltages only, neglecting capacitor and, therefore, switch voltage ripple.Likewise, the switch rms current is calculated assuming a constant current through the inductor, equal to the low-side current.The "only V ds ripple" case calculates switch voltage including the peak voltage across the switches, while the "only I ds ripple" case calculates the rms of the switch current including the sinusoidal ripple on the inductor current.The "full ripple" case includes the effects of capacitor voltage and inductor current ripples on both the switch voltage and rms current, giving the highest accuracy.The inclusion of voltage ripple in the switch stress calculation is significant, with the FCML converter seeing almost double the switch stress when at resonance (i.e., Γ = 1) compared to the calculated result when large-signal ripple is neglected.This reveals that fully resonant FCML converters may not offer the best tradeoff between passive volume and VA rating, motivating further investigation of the Fibonacci converter where applicable.
While Fig. 12 depicts solutions for the minimized total passive volume, it may be preferable to deliberately increase this volume to alleviate switch stress (volume versus efficiency tradeoff) or to extend the power range as per Table III.This expanded degree of design is illustrated in Fig. 13, where added C 0 contours in multiples of 2 n C * 0 demonstrate alternative valid operating solutions, with their corresponding switch stress and passive volume.For all topologies and provided a constant Γ, increasing the normalized capacitance above the minimizing value of C * 0 results in reduced VA rating as capacitor voltage ripple is reduced, albeit with diminishing returns for C 0 > 2C * 0 .Furthermore, although not shown, operating with a normalized capacitance less than the minimizing value C * 0 has no theoretical Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.benefit as it results in an increased passive volume, an increased VA rating, and a reduction in the achievable power throughput as a result of switch voltage clamping.Therefore, the value of C * 0 minimizing the passive volume also represents a minimum desirable choice of C 0 .
As can be observed from Fig. 13, different topologies experience varied reductions in normalized VA rating for the same relative increase in the chosen C 0 .For example, of the four topologies, the FCML sees the most dramatic reduction in VA rating, given a doubling of C 0 , whereas the series-parallel sees a much more modest decrease in VA for the same increase in capacitance.
In addition, while an energy density ratio of ρ C /ρ L = 100 was chosen for these comparisons, this ratio can vary for different capacitor and inductor technologies, as described in [1].For example, Class II ceramic capacitors (e.g., X5R) can exhibit a much higher energy density ratio of ρ C /ρ L = 1000 relative to ferrite or powder iron inductors and, therefore, may be desirable in applications that priortize power density, provided their worsened dielectric tolerances are addressed.
Finally, the optimal topology choice for a given application is dependent on available component technologies and the desired tradeoff between power density and efficiency-a classic design tradeoff.Assisting this design effort, the discussed framework provides a set of foundational analytical tools required for comprehensive large-signal design.

VIII. CONCLUSION
The metrics of VA switch stress and minimized passive component volume are highly informative to the designer when making a topology selection and designing a high-density power converter.However, with more phases and components, determining these metrics for ReSC converters becomes increasingly tedious.This article presented a concise and direct framework based on component peak energy for analyzing ReSC converters both at and above resonance, with generalized topology-dependent vectors recorded in Table VIII for convenience.In addition to providing appropriate phase durations for minimized rms currents, Section III further described a simple method to realize the complete inductor current waveform, allowing not only accurate peak required energies to be calculated but also more accurate core losses to be calculated.In addition, Table III documented each converter's maximum allowable power throughput as dictated by unintended reverse conduction in switches with increased flying capacitor voltage ripple.Section VI calculated each switch's rms current, which can be further applied to the estimation of switch-induced conduction loss, and the peak switch voltages, accounting for large voltage ripple, which can be used to accurately calculate C OSS -related switching loss.Furthermore, the presented framework significantly increased the calculation fidelity of large-signal operating points, while also offering the steps necessary for further improved loss calculation.

APPENDIX A
Throughout this article, the inductor is assumed to experience zero volt-seconds within each phase, implying that the inductor current follows a centered symmetric sinusoidal segment, beginning and ending each phase with the same current, and with the peak current occurring at the exact center of each phase.Subsequently, the relative phase durations, τ , resulting from this assumption were calculated in a simplified manner, as shown in ( 20)-( 23) and tabulated Table VIII.
However, if the assumption of per-phase zero volt-seconds is relaxed, then the inductor current waveform is not necessarily per-phase symmetric.Equations ( 20)-( 23) must then be rederived in a more generalized form to account for the possibility of some nonzero arbitrary phase shift, θ j , in each phase j.
Consider a generic resonant current waveform during phase j with peak I pk,j and arbitrary phase shift θ j i L,j (t) = I pk,j cos (ω 0,j t + θ j ) . ( The charge accumulated throughout this phase j of duration t j is then The phase-to-phase continuity equation at the transition between phase j and phase j + 1 previously presented in (20) can now also be updated to include θ j and is given by I pk,j cos ω 0,j t j 2 +θ j = I pk,j+1 cos ω 0,j+1 −t j+1 2 +θ j+1 . ( Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE VIII CHARACTERISTIC VECTORS FOR FOUR COMMON RESC TOPOLOGIES
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
Substituting (66) into (67) as before gives the same form as (23), but this expression now accounts for arbitrary phase shifts q L,j ω 0,j cos ω 0,j Applying this equation to all the pairs of adjacent phases ensures both inductor charge balance and current continuity.Therefore, any values of θ j satisfying this system of equations represent possible valid inductor current waveshapes for an ReSC converter.
Next, we determine whether any nonzero solutions for θ j exist when implementing the phase timings derived under the assumption that all θ j = 0; in other words, t j and t j+1 are known inputs, derived as per Section III and recorded as τ in Table VIII (normalized with respect to T sw ).For two-phase ReSC converters, substituting tabulated values for a L and κ into (1) and ( 19), respectively, and multiplying the result of both reveals that q L,1 ω 0,1 = q L,2 ω 0,2 . ( Similarly, substituting recorded values for τ and κ into ( 16) and (19), respectively, gives ω 0,1 t 1 = ω 0,2 t 2 . (70) Substituting ( 69) and ( 70) into (68) reveals the solution where both the phase 1-to-2 and phase 2-to-1 transitions are considered.Thus, the relative phase timings, τ , recorded in Table VIII correctly maintain both charge balance and inductor continuity.However, there exists a continuum of nonzero θ j for which these conditions are satisfied.Moreover, unless θ 1 = 0, zero volt-second per phase is not achieved.However, knowing cos(θ 1 ) = cos(|θ 2 |) and substituting (71) into (66) reveals that the peak per-phase currents I pk,j and I pk,j+1 scale with nonzero θ j , suggesting that the zero-phase solution, θ j = 0, represents a point of convergence in the presence of any real loss.To see this, the per-phase charge in (66) is rearranged to provide an expression for the peak current I pk,j = q L,j ω 0,j 2 cos(θ j ) sin Here, peak current is minimized when cos(θ j ) is at its maximum value (i.e., when θ j = 0).This is visualized in Fig. 14(a) for an N = 2 FCML both at θ j = 0 and θ j = π/8 rad, where both the waveforms satisfy charge balance and current continuity.From inspection, θ j = 0 minimizes the peak, peak-to-peak, and rms current.Therefore, similar to the conclusions in [72], we conjecture that parasitic loss mechanisms will minimize the circuit losses by ensuring that any inductor current initialized with some nonzero values of θ j will converge to the zero phase-shift Fig. 14.Inductor current waveforms at Γ = 1.5 for an FCML converter with varied conversion ratio N and corresponding number of phases N P = N .Sweeping phase angle θ between 0 and π/8 rad while constraining constant charge q L -i.e., keeping the accumulated area in each phase fixeddemonstrates that the peak, peak-to-peak, and rms currents are all minimized when θ j = 0.For odd N , inductor continuity cannot be satisfied for θ j = 0.
condition (θ j = 0) in steady state, implying a symmetrically centered current waveform in each phase and adherence to the per-phase zero volt-second assumption applied throughout the article.Finally, while zero inductor volt-second per phase (i.e., θ j = 0) is merely assumed for a general ReSC converter, for odd-N FCML converters, this condition is necessary and corresponds to the only valid operating state where both steady-state charge balance and inductor current continuity are satisfied.To illustrate this, Fig. 14 plots steady-state inductor current waveforms for three conversion ratios, i.e., a) N = 2, b) N = 3, and c) N = 4, where for the FCML converter, the conversion ratio also equals the number of phases, N P .As is apparent in Fig. 14(b) for an odd value of N , nonzero values of θ j will result in a current discontinuity, thus violating periodic steady state.Therefore, for FCML converters with odd N , nonzero values of θ j do not result in valid operating conditions, implying that the inductor must Fig. 15.Exemplar capacitor voltage and current waveforms for the given normalized charge flow vector a C,1 in (74).The capacitor is charged by quantity q HI in phases 1 and 4, and discharged by quantity q HI in Phases 2 and 3.For simplicity, constant capacitor current and linear capacitor voltage are shown.
experience zero volt-seconds within each phase in steady state.This outcome further supports the conclusions made in [52] and [75] and is observed experimentally in Section V, where measured inductor current waveforms for N = 5 express near perfect zero volt-second per phase behavior.

APPENDIX B
Section IV-A introduces a modified charge flow quantity, âC,i , defined as the maximum deviation in stored charge on the ith flying capacitor throughout a full switching cycle.This quantity is simplified for the ReSC cases presented in this article; however, a more generalized expression âC,i = max is applicable to any charge flow vector, a C , so long as it satisfies the periodic steady-state condition in (3).The first term determines the peak positive (maximum) accumulated charge, while the second term determines the peak negative (minimum) accumulated charge.The difference between these values is the peak-to-peak charge ripple experienced by the capacitor.
Consider an example calculation of âC,1 for a capacitor C 1 that experiences some arbitrary normalized capacitor charge flow vector A possible capacitor current waveform, i C,1 (t), corresponding to this charge vector, and its associated voltage waveform, v C,1 (t), are shown in Fig. 15, where a constant current during each phase is assumed for simplicity.The capacitor voltage ripple is centered around the mid-range voltage, V C 1 , while the capacitor current is centered around zero to satisfy periodic steady-state conditions.The charge expelled or received per phase corresponds to the area under the current waveform during that phase and has a magnitude of q HI as per (1).By inspecting Fig. 15 or evaluating (73), we can determine that the peak positive accumulated charge occurs at the end of phase j = 1, and the peak negative accumulated charge occurs at the end of phase j = 3 This value can then be substituted into (39) to find the peak-topeak voltage ripple, Δv pp,1 , for capacitor C 1 (also depicted in Fig. 15).

Fig. 5 .
Fig. 5. Numerical solution of relative phase durations τ 1 and τ 2 for a 5:1 FCML converter across Γ.The closed-form approximations are superimposed with dashed lines and differ by less than 0.03% of the switching period.

Fig. 6 .
Fig. 6.Simulated inductor current waveforms i L (t) for a 5:1 resonant FCML converter, demonstrating the required change in phase durations as a function of Γ.

Fig. 7 .
Fig. 7. Normalized minimum total passive volume versus conversion ratio for ρ C /ρ L = 100, and 1 ≤ Γ < ∞.The range of Γ is annotated for the Dickson topology only, but applies similarly for all topologies plotted.For Γ > 5, diminishing ripple reductions result in minimal reductions in volume.

Fig. 8 .
Fig. 8. Annotated photograph of the FCML converter used to validate the passive volume calculations.Constructed on a white soldermask, the hardware presented in [21] is modified to include the passive component cases depicted in Fig. 9.

Fig. 9 .
Fig. 9.Total passive component volume for three different 5:1 FCML converter solutions with identical resonant switching frequency.P HI = 77 W, Γ = 1.25, f sw = 250 kHz, and V HI = 200 V.All the components are depicted to relative scale.For Case 2, C 0 = C * 0 = 44 nF, resulting in approximately minimal total component volume.

Fig. 10 .
Fig. 10.Total measured passive volume versus C * 0 for three constructed cases, along with theoretically derived continuous functions of (53) with and without a 10% passive component derating.The error between measured and theoretical datapoints results from practical component rating availability.Minimizing capacitance C * 0 is highlighted, illustrating that even with imperfect component selection, a minimized result is still achieved.

Fig. 11 .
Fig. 11.Measured flying capacitor voltage waveforms (top), inductor current (middle), and switch voltages, V ds (bottom) for minimized volume Case 2, where V HI = 200 V, P HI = 77 W, f sw = 250 kHz, and Γ = 1.25.Switches are controlled in accordance with the clocking scheme depicted in Fig.4with phase timing durations calculated using(35) and(36).For each phase, the inductor current waveform is a centered symmetric sinusoidal segment, further validating the zero volt-seconds per phase assumption.

Fig. 11
depicts measured flying capacitor voltage and inductor current waveforms at the described operating point with C 0 = C * 0 = 44 nF and L = L * = 3.4 µH.Taking measured peak inductor current, peak flying capacitors voltages, and applying 1 2 LI 2 pk and 1 2 C 0 V 2 pk reveals total peak inductor and capacitor energies of 14.3 µJ and 1.4 mJ, respectively.Dividing by passive energy densities ρ L and ρ C yields the theoretically expected minimum volume of Vol * tot = 275 mm 3 , as predicted by (

Fig. 13 .
Fig.13.Normalized switch VA rating versus normalized total passive volume with relative energy density ratio ρ C /ρ L = 100.Full ripple is assumed on all passives for improved accuracy.Added curves demonstrate a reduction in total switch stress with increasing passive volume within a given converter solution.

,
Manuscript received 16 February 2023; revised 22 April 2023; accepted 27 May 2023.Date of publication 21 June 2023; date of current version 16 May 2024.Recommended for publication by Associate Editor Carl N.M.Ho.Parts of the analysis in Section III of this article were presented at the 2022 IEEE 23rd Workshop on Control and Modeling for Power Electronics [DOI: 10.1109/COMPEL53829.2022.9830004].(Corresponding author: Robert C. N. Pilawa-Podgurski.)

TABLE I SURVEY
OF ANALYTICAL METHODS FOR SC CONVERTERS control

TABLE VI UNIT
PASSIVE COMPONENT DETAILS