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    <title>Recent ucsd_cse_technicalreports items</title>
    <link>https://escholarship.org/uc/ucsd_cse_technicalreports/rss</link>
    <description>Recent eScholarship items from Technical Reports</description>
    <pubDate>Mon, 31 Aug 2026 21:29:16 +0000</pubDate>
    <item>
      <title>Comparative Effectiveness of Coaching Modalities in Commercial Fleet Operations</title>
      <link>https://escholarship.org/uc/item/5969f87m</link>
      <description>&lt;p&gt;This report presents findings from a comprehensive survey of commercial fleet professionals involved in fleet safety (specifically managers, coaches and decision-makers) regarding the perceived effectiveness, practical implementation, and strategic value of different driver coaching approaches. Grounded in the broader objective of improving safety outcomes through evidence-based coaching strategies, the survey sought to explore both individual preferences and organizational practices.&lt;/p&gt;&lt;p&gt;The survey respondents consisted of two distinct groups: individuals who identify coaching as a key part of their primary job, and commercial dashcam decision-makers who do not directly engage in driver coaching. This composition allowed for insights from both those actively involved in coaching practices and those responsible for implementing or overseeing dashcam technology without hands-on coaching responsibilities.&lt;/p&gt;</description>
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      <pubDate>Tue, 11 Nov 2025 00:00:00 +0000</pubDate>
      <author>
        <name>Weibel, Nadir</name>
      </author>
      <author>
        <name>Yarmand, Matin</name>
      </author>
      <author>
        <name>Biehle, Cole</name>
      </author>
      <author>
        <name>Mac, Elysia</name>
      </author>
      <author>
        <name>Lu, Huimeng</name>
      </author>
      <author>
        <name>Xiang, Vivian</name>
      </author>
      <author>
        <name>Strudler, Gabriella</name>
      </author>
      <author>
        <name>Hathiram, Pari</name>
      </author>
    </item>
    <item>
      <title>Evaluating and Optimizing Coaching Methodologies for Fleet Safety and Performance: An Evidence-Based Analysis of Differentiation and Optimization Opportunities</title>
      <link>https://escholarship.org/uc/item/1z82z8pg</link>
      <description>&lt;p&gt;This report critically evaluates coaching methodologies for enhancing fleet driver safety, engagement, and overall organizational performance. Drawing on empirical research across education, behavioral science, and fleet management, this analysis identifies key dimensions of effective commercial driver coaching, highlights significant limitations of current practices, and outlines strategic recommendations focused explicitly on differentiation and optimization. The findings emphasize the superior effectiveness of personalized, manager-led coaching methods, yet also show how manager-led coaching alone is challenging to implement at scale given the scarce availability of expert coaches. On the other hand, this report shows that in-cabin automated warning systems and self-coaching offer strengths in scalability and flexible learning. However, without integration with more personalized and interactive feedback, these approaches alone do not achieve the same long-term safety outcomes...</description>
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      <pubDate>Mon, 30 Jun 2025 00:00:00 +0000</pubDate>
      <author>
        <name>Weibel, Nadir</name>
      </author>
      <author>
        <name>Yarmand, Matin</name>
      </author>
      <author>
        <name>Biehle, Cole</name>
      </author>
      <author>
        <name>Mac, Elysia</name>
      </author>
      <author>
        <name>Lu, Huimeng</name>
      </author>
      <author>
        <name>Xiang, Vivian</name>
      </author>
    </item>
    <item>
      <title>Review of “Laser soliton microcombs heterogeneously integrated on silicon” at a Introductory Graduate Laser Course Level</title>
      <link>https://escholarship.org/uc/item/29d3b140</link>
      <description>&lt;p&gt;In this paper review, I will explain the fundamentals of a “laser soliton microcomb heterogeneously integrated on silicon”, presented by Xiang et. al of the Bowers Lab at UCSB [1]. I will try to relate concepts taught in class, which will be &lt;strong&gt;bolded&lt;/strong&gt;, while presenting new material at a level that can be understood by someone who only has understanding of basic optics as well as the theory, components, and operation of a traditional Fabry-Perot cavity laser.&lt;/p&gt;&lt;p&gt;In this paper Xiang et. al present the design, the underlying photonics principles used, their fabrication process and considerations, and finally performance measurements and verification of the final device.&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/29d3b140</guid>
      <pubDate>Tue, 7 Jan 2025 00:00:00 +0000</pubDate>
      <author>
        <name>Ding, Jerry</name>
      </author>
    </item>
    <item>
      <title>Augmenting Telepostpartum Care With Vision-Based Detection of Breastfeeding-Related Conditions: Algorithm Development and Validation</title>
      <link>https://escholarship.org/uc/item/610345mv</link>
      <description>&lt;p&gt;&lt;strong&gt;Background:&amp;nbsp;&lt;/strong&gt;Breastfeeding benefits both the mother and infant and is a topic of attention in public health. After childbirth, untreated medical conditions or lack of support lead many mothers to discontinue breastfeeding. For instance, nipple damage and mastitis affect 80% and 20% of US mothers, respectively. Lactation consultants (LCs) help mothers with breastfeeding, providing in-person, remote, and hybrid lactation support. LCs guide, encourage, and find ways for mothers to have a better experience breastfeeding. Current telehealth services help mothers seek LCs for breastfeeding support, where images help them identify and address many issues. Due to the disproportional ratio of LCs and mothers in need, these professionals are often overloaded and burned out.&lt;/p&gt;&lt;p&gt;&lt;strong&gt;Objective:&amp;nbsp;&lt;/strong&gt;This study aims to investigate the effectiveness of 5 distinct convolutional neural networks in detecting healthy lactating breasts and 6 breastfeeding-related...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/610345mv</guid>
      <pubDate>Tue, 19 Nov 2024 00:00:00 +0000</pubDate>
      <author>
        <name>de Souza, Jessica</name>
      </author>
      <author>
        <name>Kumar Viswanath, Varun</name>
      </author>
      <author>
        <name>Echterhoff, Jessica Maria</name>
      </author>
      <author>
        <name>Chamberlain, Kristina</name>
      </author>
      <author>
        <name>Wang, Edward Jay</name>
      </author>
    </item>
    <item>
      <title>Preble: Efficient Distributed Prompt Scheduling for LLM Serving</title>
      <link>https://escholarship.org/uc/item/1bm0k1w0</link>
      <description>&lt;p&gt;Prompts to large language models (LLMs) have evolved beyond simple user questions. For LLMs to solve complex problems, today's practices are to include domain-specific instructions, illustration of tool usages, and long context such as textbook chapters in prompts. As such, many parts of prompts are repetitive across requests, and their attention computation results can be reused. However, today's LLM serving systems treat every request in isolation, missing the opportunity of computation reuse.&lt;/p&gt;&lt;p&gt;This paper proposes Preble, the first distributed LLM serving platform that targets and optimizes for prompt sharing. We perform a study on five popular LLM workloads. Based on our study results, we designed a distributed scheduling system that co-optimizes computation reuse and load balancing. Our evaluation of Preble on two to 8 GPUs with real workloads and request arrival patterns on two open-source LLM models shows that Preble outperforms the state of the art avg latency by...</description>
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      <pubDate>Fri, 17 May 2024 00:00:00 +0000</pubDate>
      <author>
        <name>Srivatsa, Vikranth</name>
      </author>
      <author>
        <name>He, Zijian</name>
      </author>
      <author>
        <name>Abhyankar, Reyna</name>
      </author>
      <author>
        <name>Li, Dongming</name>
      </author>
      <author>
        <name>Zhang, Yiying</name>
      </author>
    </item>
    <item>
      <title>Analysis of Targeted Advertising in Snapchat Political Ads</title>
      <link>https://escholarship.org/uc/item/8gc2k3kw</link>
      <description>Snapchat is one of the most popular social media apps in the world. It is no surprise, then, that many political ads are run on the service each year. Snap Inc.'s political ads library is part of an effort by the company to increase transparency in their advertising practices. The data analyzed in this project spans 2019-2020, and consists of information on every political ad that was run on the service in that timeframe, including who the ad buyer was, how much the ad cost, what areas it targeted, etc. Geographic and monetary distribution of ads is analyzed and possible explanations given for anomalies. Missingness of the data was evaluated and Vermont was identified as an area with unusual spending. With&amp;nbsp;α&amp;nbsp;= 0.05 the null hypothesis was rejected (p&amp;nbsp;= 0.02); the distribution of ad dollars to Vermont is not wholly random.</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8gc2k3kw</guid>
      <pubDate>Thu, 16 May 2024 00:00:00 +0000</pubDate>
      <author>
        <name>Gorlla, Cyril</name>
      </author>
    </item>
    <item>
      <title>Development of Algorithm to Predict Political Ad Spending on Snapchat</title>
      <link>https://escholarship.org/uc/item/6413d1xx</link>
      <description>The Snapchat ads dataset contains political ad data for ads on Snapchat, oneof the largest social media networks in the world. A key feature of the datasetis how much money an organization spends on a particular ad, found in the`Spend` column. It is reasonable to assume that this amount varies based oncertain factors, but can we use those factors to figure out how much is spenton an ad? We can explore this by predicting ad spending through machinelearning. After feature analysis and engineering, we arrive at a linearregression model with $R^2$ = .85 and perform a fairness evaluation of thealgorithm.</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6413d1xx</guid>
      <pubDate>Thu, 16 May 2024 00:00:00 +0000</pubDate>
      <author>
        <name>Gorlla, Cyril</name>
      </author>
    </item>
    <item>
      <title>Surface Reconstruction from Points</title>
      <link>https://escholarship.org/uc/item/9xv8x6n6</link>
      <description>This report surveys recent techniques for reconstructing surfaces
from points. We describe four main ideas in the graphics literature: signed
distance estimation, Voronoi-based reconstruction, implicit surface fitting,
and moving least squares surfaces. The main challenges include reconstruction
without surface normals, robustness to noise, accuracy to sharp features, and
provable reconstruction guarantees. We compare various techniques and discuss
possible avenues for future work.&lt;p&gt;Pre-2018 CSE ID: CS2008-0922&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9xv8x6n6</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Chang, William Y</name>
      </author>
    </item>
    <item>
      <title>Ming II: A Flexible Platform for NAND Flash-based Research</title>
      <link>https://escholarship.org/uc/item/9x77f916</link>
      <description>NAND flash-based solid-state drives (SSDs) are becoming a staple in
consumer electronics and high-performance computing. Limited resources and a
lack of flexible prototyping platforms constrain NAND flash researchers to use
software simulation of the chips, where simulation parameters are based on
conservative values from datasheets, leading to missed research opportunities.
A tool to explore low-level NAND flash behavior and performance would give
researchers an easy way to validate and guide new research ideas and designs.
We present the Ming II platform which gives researchers complete control over
flash chips. It includes a custom board that connects to a platform FPGA system
and provides an automated interface for acquiring fine-grain power, latency,
and bit error measurements of flash operations. The Ming II software stack
includes an open-source userspace library, Linux driver, and development
environment that make it easy to develop new software that targets flash.
Possible...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9x77f916</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Bunker, Trevor</name>
      </author>
      <author>
        <name>Wei, Michael</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>CitiSense - Adaptive Services for Community-Driven Behavioral and Environmental Monitoring to Induce Change</title>
      <link>https://escholarship.org/uc/item/9wx7m5z6</link>
      <description>In this work we present CitiSense, a new kind of "citizen
infrastructure" for the monitoring of pollution and environmental conditions
that users are exposed to. By utilizing mobile phones and affordable, small
sensors placed in the environment and carried by users, data about pollutants
such as ozone and carbon monoxide is collected and used to provide real-time
feedback to users and enable them to make healthy changes in their behavior.
Results can be reported to a back-end server for further processing and
learning, allowing other stakeholders to better understand how diseases such as
asthma develop and to help coordinate efforts within a user's community to
improve conditions. What differentiates CitiSense from previous projects of
this sort is the design of a complete system that addresses issues of mobile
power management, data security, privacy, inference with commodity sensors, and
integration into a highly extensible and adaptive infrastructure comprising of
Open Rich...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9wx7m5z6</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Nikzad, Nima</name>
      </author>
      <author>
        <name>Ziftci, Celal</name>
      </author>
      <author>
        <name>Zappi, Piero</name>
      </author>
      <author>
        <name>Quick, Nichole</name>
      </author>
      <author>
        <name>Aghera, Priti</name>
      </author>
      <author>
        <name>Verma, Nakul</name>
      </author>
      <author>
        <name>Demchak, Barry</name>
      </author>
      <author>
        <name>Patrick, Kevin</name>
      </author>
      <author>
        <name>Shacham, Hovav</name>
      </author>
      <author>
        <name>Rosing, Tajana Simunic</name>
      </author>
      <author>
        <name>Krueger, Ingolf</name>
      </author>
      <author>
        <name>Griswold, William G</name>
      </author>
      <author>
        <name>Dasgupta, Sanjoy</name>
      </author>
    </item>
    <item>
      <title>Verilogo: Proactive Phishing Detection via Logo Recognition</title>
      <link>https://escholarship.org/uc/item/9tq826n1</link>
      <description>Defending users against fraudulent Websites (i.e., phishing) is a
task that is reactive in practice.  Blacklists, spam filters, and takedowns all
depend on first finding new sites and verifying that they are fraudulent.  In
this paper we explore an alternative approach that uses a combination of
computer-vision techniques to proactively identify likely phishing pages as
they are rendered, interactive queries to validate such pages with brand
holders, and a single keyboard-entry filter to minimize false positives.  We
have developed a prototype version of this approach within the Firefox browser
and we provide a preliminary evaluation of both the underlying technology (the
accuracy and performance of logo recognition in Web pages) as well as its
effectiveness in controlled small-scale user studies. While no such approach is
perfect, our results demonstrate that this technique offers a significant new
capability for minimizing response time in combating a wide range of phishing
scams.&lt;p&gt;Pre-2018...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9tq826n1</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Wang, Ge</name>
      </author>
      <author>
        <name>Liu, He</name>
      </author>
      <author>
        <name>Becerra, Sebastian</name>
      </author>
      <author>
        <name>Wang, Kai</name>
      </author>
      <author>
        <name>Belongie, Serge</name>
      </author>
      <author>
        <name>Shacham, Hovav</name>
      </author>
      <author>
        <name>Savage, Stefan</name>
      </author>
    </item>
    <item>
      <title>The Beam Radiance Estimate for Volumetric Photon Mapping</title>
      <link>https://escholarship.org/uc/item/9nz3j133</link>
      <description>We present a new method for efficiently simulating the scattering of
light within participating media. Using a theoretical reformulation of
volumetric photon mapping, we develop a novel photon gathering technique for
participating media. Traditional volumetric photon mapping samples the
in-scattered radiance at numerous points along the length of a single ray by
performing costly range queries within the photon map. Our technique replaces
these multiple point-queries with a single beam-query, which explicitly gathers
all photons along the length of an entire ray. These photons are used to
estimate the accumulated in-scattered radiance arriving from a particular
direction and need to be gathered only once per ray. Our method handles both
fixed and adaptive kernels, is faster than regular volumetric photon mapping,
and produces images with less noise.&lt;p&gt;Pre-2018 CSE ID: CS2008-0914&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9nz3j133</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Jarosz, Wojciech</name>
      </author>
      <author>
        <name>Zwicker, Matthias</name>
      </author>
      <author>
        <name>Jensen, Henrik Wann</name>
      </author>
    </item>
    <item>
      <title>Random projection trees and low dimension manifolds</title>
      <link>https://escholarship.org/uc/item/9jh7v86q</link>
      <description>We present a simple variant of the k-d tree which automatically
adapts to intrinsic low dimensional structure in data without having to
explicitly learn this structure.&lt;p&gt;Pre-2018 CSE ID: CS2007-0890&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9jh7v86q</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Dasgupta, Sanjoy</name>
      </author>
      <author>
        <name>Freund, Yoav</name>
      </author>
    </item>
    <item>
      <title>Iago Attacks: Why The System Call API Is a Bad Untrusted RPC Interface</title>
      <link>https://escholarship.org/uc/item/9dw8h2t7</link>
      <description>In recent years, researchers have proposed systems for running
trusted code on an untrusted operating system. Protection mechanisms deployed
by such systems keep a malicious kernel from directly manipulating a trusted
application’s state. Under such systems, the application and kernel are,
conceptually, peers, and the system call API defines an RPC interface between
them. We introduce Iago attacks, attacks that a malicious kernel can mount in
this model. We show how a carefully chosen sequence of integer return values to
Linux system calls can lead a supposedly protected process to act against its
interests, and even to undertake arbitrary computation at the malicious
kernel’s behest. Iago attacks are evidence that protecting applications from
malicious kernels is more difficult than previously realized.&lt;p&gt;Pre-2018 CSE ID: CS2012-0984&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9dw8h2t7</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Checkoway, Steven</name>
      </author>
      <author>
        <name>Shacham, Hovav</name>
      </author>
    </item>
    <item>
      <title>Universal Honeyfarm Containment</title>
      <link>https://escholarship.org/uc/item/9dj789fj</link>
      <description>The growing sophistication of self-propagating worms and botnets
presents a significant challenge for investigators to understand. While
honeyfarms have emerged as a powerful tool for capturing and analyzing rapid
malware, the size and complexity of large scale, high fidelity honeyfarms make
them problematic to operate in a simultaneously safe and effective manner. This
paper introduces a universe abstraction that guarantees isolation between
multiple malware infestations in a single honeyfarm while maximizing the
realism of the honeyfarm as observed by a propagating worm. We demonstrate that
each malware strain can be completely isolated without distorting malware
spreading behavior, and that this can in fact increase the scalability of
honeyfarms.&lt;p&gt;Pre-2018 CSE ID: CS2007-0902&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9dj789fj</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Chen, Jay</name>
      </author>
      <author>
        <name>McCullough, John</name>
      </author>
      <author>
        <name>Snoeren, Alex C</name>
      </author>
    </item>
    <item>
      <title>CAPTCHA-based Image Labeling on the Soylent Grid</title>
      <link>https://escholarship.org/uc/item/9dh0r7hf</link>
      <description>We introduce an open labeling platform for Computer Vision
researchers based on Captchas, creating as a byproduct labeled image data sets
while supporting web security. For the two diﬀerent tasks of annotation and
detection, we provide a security analysis and explore usability issues. We
present the interfaces used by researchers, website administrators and users
and experimental results obtained using the platform. Finally, we discuss
system sustainability issues in the context of a broader “ecosystem” for
the platform.&lt;p&gt;Pre-2018 CSE ID: CS2009-0942&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9dh0r7hf</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Faymonville, Peter</name>
      </author>
      <author>
        <name>Wang, Kai</name>
      </author>
      <author>
        <name>Miller, John</name>
      </author>
      <author>
        <name>Belongie, Serge</name>
      </author>
    </item>
    <item>
      <title>Programming Bulk-Incremental Dataflows</title>
      <link>https://escholarship.org/uc/item/9bx1c3pk</link>
      <description>Government, medical, financial, and web-based services increasingly
depend on the ability to rapidly sift through huge, evolving data sets. These
data-intensive applications perform complex multi-step computations over
successive generations of data inflows (e.g., weekly web crawls, nightly
telescope dumps, or hourly surveillance videos). Because of the data volumes
involved, applications must avoid reprocessing old data when new data arrives
and instead process incrementally. Unlike in stream-based systems, incoming
data does not have to be processed immediately, permitting work to be amortized
via bulk processing. Such bulk-incremental processing represents an emerging
class of applications whose needs are not fully met by current systems. This
paper presents a generalized architecture for bulk-incremental processing
systems (BIPS), simplifying the creation of such programs. In contrast with
incremental view maintenance in data warehousing, BIPS provides flexible
low-level primitives...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9bx1c3pk</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Logothetis, Dionysios</name>
      </author>
      <author>
        <name>Olston, Christofer</name>
      </author>
      <author>
        <name>Reed, Benjamin</name>
      </author>
      <author>
        <name>Webb, Kevin</name>
      </author>
      <author>
        <name>Yocum, Kenneth</name>
      </author>
    </item>
    <item>
      <title>An Analysis of Scaling in QuickSAN</title>
      <link>https://escholarship.org/uc/item/9bm5k56q</link>
      <description>Solid State Disks (SSDs) based on flash and other non-volatile
memory technologies reduce storage latencies from 10s of milliseconds to 10s or
100s of microseconds, transforming previously inconsequential storage overheads
into performance bottlenecks. This problem is especially acute in storage area
network (SAN) environments where complex hardware and software layers
(distributed file systems, block severs, network stacks, etc.) lie between
applications and remote data. These layers can add hundreds of microseconds to
requests, obscuring the performance of both flash memory and faster, emerging
non-volatile memory technologies. This work examines the performance of
QuickSAN, a SAN prototype that eliminates most software overheads and
significantly reduces hardware overheads in SANs, as the number of nodes in the
SAN increases. QuickSAN integrates a network adapter directly into SSDs, so the
SSDs can communicate directly with one another to service storage accesses as
quickly...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9bm5k56q</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Caulfield, Adrian M</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>Slicing Spam with Occam's Razor</title>
      <link>https://escholarship.org/uc/item/9622h33g</link>
      <description>To evade blacklisting, the vast majority of spam email is sent from
exploited MTAs (i.e., botnets) and with forged "From" addresses.  In response,
the anti-spam community has developed a number of domain-based authentication
systems -- such as SPF and DKIM -- to validate the binding between individual
domain names and legitimate mail sources for those domains.  In this paper, we
explore an alternative solution in which the mail recipient requests a
real-time affirmation for each e-mail from the declared sender's MX of record.
The "Occam" protocol is trivial to implement, offers authenticating power
equivalent to SPF and DKIM and, most importantly, forces spammers to deploy and
expose blacklistable servers for each domain they use during a campaign.  We
discuss the details of the protocol, compare its strengths and weaknesses with
existing solutions and describe a prototype implementation in Sendmail.&lt;p&gt;Pre-2018 CSE ID: CS2007-0893&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9622h33g</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Fleizach, Chris</name>
      </author>
      <author>
        <name>Voelker, Geoffrey M</name>
      </author>
      <author>
        <name>Savage, Stefan</name>
      </author>
    </item>
    <item>
      <title>Reducing Datacenter Application Latency with Endhost NIC Support</title>
      <link>https://escholarship.org/uc/item/95x5m073</link>
      <description>In datacenter applications, predictability in service time and
controlled latency, especially tail latency, is essential for building
performant applications.  This is especially true for applications or services
build by accessing data across thousands of servers to generate a user
response.  Current practice has been to run such services at low utilization to
rein in latency outliers, which decreases efficiency and limits the number of
service invocations developers can issue while still meeting tight latency
budgets. In this paper, we analyze the three datacenter applications,
Memcached, OpenFlow, and web search, to measure the effect on tail latency of
1) kernel socket handling, NIC interaction, and the network stack, 2)
application locks contested in the kernel, and 3) application-layer queuing due
to requests being stalled behind straggler threads.  We propose a novel
approach of reducing the above sources of latency by relying on support from
the NIC hardware, and we find...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/95x5m073</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Kapoor, Rishi</name>
      </author>
      <author>
        <name>Porter, George</name>
      </author>
      <author>
        <name>Tewari, Malveeka</name>
      </author>
      <author>
        <name>Voelker, Geoffrey M</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
    </item>
    <item>
      <title>FPGA Implementation of Adaptive Weight Calculation Core Using QRD-RLS Algorithm</title>
      <link>https://escholarship.org/uc/item/9514v2jb</link>
      <description>We present a novel architecture for adaptive weight calculation
(AWC) that uses the QR decomposition based recursive least squares (RLS)
algorithm. Our AWC core achieves a throughput of 0.20M updates per second for a
4 x 4 matrix on a Xilinx Virtex4 SX FPGA. We show that our core is
significantly faster than other published FPGA implementations and it requires
fewer resources. This is largely a consequence of careful error analysis that
allows us to take advantage of a fixed point data representation with little
degradation in the final results. Finally, our proposed architecture scales
well for larger size matrices.&lt;p&gt;Pre-2018 CSE ID: CS2009-0937&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9514v2jb</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Irturk, Ali</name>
      </author>
      <author>
        <name>Mirzaei, Shahnam</name>
      </author>
      <author>
        <name>Kastner, Ryan</name>
      </author>
    </item>
    <item>
      <title>Deterministic Replay using Processor Support and Its Applications</title>
      <link>https://escholarship.org/uc/item/9490c7h1</link>
      <description>The processor industry is at an inflection point. In the past,
performance was the driving force behind the processor industry. But in the
coming manycore era, improving programmability and reliability of the system
will be at least as important as improving raw performance. To meet this
vision, this thesis presents a processor feature that assists programmers in
understanding software failures. &lt;p&gt; Reproducing software failures is a
significant challenge. The problem is severe especially for multi-threaded
programs because the causes of failure can be non-deterministic in nature. The
proposed processor feature continuously logs a program.s execution while
sacrificing very little performance ( 1%). If the program crashes, the
developer can use the log to debug the failure by deterministically replaying
every single instruction executed as part of the failed program.s execution.
Two key mechanisms enable this deterministic replay feature. One is BugNet, a
checkpointing technique,...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9490c7h1</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Narayanasamy, Satish</name>
      </author>
    </item>
    <item>
      <title>Automatically Mining Requirements Relationships From Test Cases</title>
      <link>https://escholarship.org/uc/item/9357z8vg</link>
      <description>Requirements relationships express conceptual dependencies,
constraints and associations among the requirements of a software system, such
as dependencies and hint-relations. For stakeholders of a system, it is
important and beneficial to identify requirements relationships for system
design, maintenance and comprehension tasks. In this paper, we build on
existing research and use features, realization of functional requirements in
software, to automatically retrieve requirements relationships from existing
test cases. We evaluate our approach on a chat system, Apache Pool, and Apache
Commons CLI. We obtain precision/recall levels as good as or better than
currently existing object-tracing and scenario-analysis based approaches when
tested on the same case studies. Furthermore, our approach is resistant to
scenario selection, and works for all types of systems with a profiler
available, unlike existing techniques.&lt;p&gt;Pre-2018 CSE ID: CS2013-1001&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9357z8vg</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Ziftci, Celal</name>
      </author>
      <author>
        <name>Krueger, Ingolf</name>
      </author>
    </item>
    <item>
      <title>Hardening the NOVA File System</title>
      <link>https://escholarship.org/uc/item/9278h2ww</link>
      <description>Emerging fast, persistent memories will enable systems that combine conventional DRAM with large amounts of non-volatile main memory (NVMM) and provide huge increases in storage performance. Fully realizing this potential requires fundamental changes in how system software manages, protects, and provides access to data that resides in NVMM. We address these needs by describing a NVMM-optimized file system called NOVA that is both fast and resilient in the face of corruption due to media errors and software bugs. We identify and propose solutions for the unique challenges in hardening an NVMM file system, adapt state-of-the-art reliability techniques to an NVMM file system, and quantify the performance and storage overheads of these techniques. We find that NOVA's reliability features increase file system size system size by 14.9% and reduce application-level performance by between 2% and 38%.&lt;p&gt;Pre-2018 CSE ID: CS2017-1018&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9278h2ww</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Xu, Jian</name>
      </author>
      <author>
        <name>Zhang, Lu</name>
      </author>
      <author>
        <name>Memaripour, Amirsaman</name>
      </author>
      <author>
        <name>Gangadharaiah, Akshatha</name>
      </author>
      <author>
        <name>Borase, Amit</name>
      </author>
      <author>
        <name>Brito Da Silva, Tamires</name>
      </author>
      <author>
        <name>Rudoff, Andy</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>Clock Synchronization with Deterministic Accuracy Guarantee</title>
      <link>https://escholarship.org/uc/item/9130p3t5</link>
      <description>Accuracy is one of the most important performance metrics in clock
synchronization. While state-of-the-art synchronization protocols achieve
μsec-order average accuracy, they usually do not focus on the worst case
accuracy and do not have any deterministic guarantees. This lack of accuracy
guarantee makes it hard for sensor networks to be incorporated into larger
systems that require more reliability than e.g., typical environmental
monitoring applications do. In this paper, we present a clock synchronization
algorithm with deterministic accuracy guarantee. A key observation is that the
variability of oscillation frequency is much smaller in a single crystal than
between different crystals. Our algorithm leverages this to achieve much
tighter accuracy guarantee compared to the interval-based synchronization
methods mostly proposed in the literature of distributed systems. We designed
an algorithm to solve a geometric problem involving tangents to convex
polygons, and implemented...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/9130p3t5</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Sugihara, Ryo</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Interactive Visual Exploration of Service Level Objectives</title>
      <link>https://escholarship.org/uc/item/8z62z06f</link>
      <description>Service Level Objectives (SLOs) describe the desired behavior of a
service. They present agreed-upon target behaviors (e.g. capacity, performance,
availability, cost) that the clients of a service can expect, and that the
service provider can manage against. Both clients and service providers need a
way to monitor how a service is doing against its SLOs, and display the result
of that monitoring in an intuitive fashion. This paper describes a tool that
provides interactive visual exploration for services; makes it easy to navigate
around the multi-dimensional space of services, their instances, users, and
metrics; and is driven by the machine-readable description of the SLO itself,
so that changes can be propagated automatically. The contributions of the paper
include a description of the requirements and implementation of our system; the
techniques used to display aspects of --- and navigate around --- the
multi-dimensional space; and how the SLOs are used to automate the display...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8z62z06f</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Kim, Han Suk</name>
      </author>
      <author>
        <name>Verma, Sunita</name>
      </author>
      <author>
        <name>Wilkes, John</name>
      </author>
    </item>
    <item>
      <title>QuickSAN: A Storage Area Network for Fast, Distributed, Solid State Disks</title>
      <link>https://escholarship.org/uc/item/8x74g752</link>
      <description>Solid State Disks (SSDs) based on flash and other non-volatile
memory technologies reduce storage latencies from 10s of milliseconds to 10s or
100s of microseconds, transforming previously inconsequential storage overheads
into performance bottlenecks.  This problem is especially acute in storage area
network (SAN) environments where complex hardware and software layers
(distributed file systems, block severs, network stacks, etc.) lie between
applications and remote data.  These layers can add hundreds of microseconds to
requests, obscuring the performance of both flash memory and faster, emerging
non-volatile memory technologies. We describe QuickSAN, a SAN prototype that
eliminates most software overheads and significantly reduces hardware overheads
in SANs.  QuickSAN integrates a network adapter directly into SSDs, so the SSDs
can communicate directly with one another to service storage accesses as
quickly as possible. QuickSAN can also give applications direct access to both
local...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8x74g752</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Caulfield, Adrian M</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>The Role of End-to-End Congestion Control in Networks with Fairness-Enforcing Routers</title>
      <link>https://escholarship.org/uc/item/8ws91483</link>
      <description>Traditionally, capacity on the Internet has been allocated between
competing flows through a distributed fairness calculation implemented by
end-to-end congestion control protocols like TCP. Increasingly, however,
network operators are deploying fair queuing and other forms of router-based
enforcement mechanisms to prevent greedy or misbehaving end points from
consuming more than their fair share of the network’s capacity. In
environments where fairness is enforced by the network itself, it seems
worthwhile to reconsider the role of the congestion control protocol. In
particular, we ask if it might be both safe and sensible in the long term for
self-interested senders to send at rates that exceed the capacity of the
network. Through simulation, we identify and quantify the source of
inefficiency in this regime, which we term zombie packets. Surprisingly, we
show that such aggressive mechanisms are not only tenable in a wide variety of
network structures, but, combined with effective...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8ws91483</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Raghavan, Barath</name>
      </author>
      <author>
        <name>McCollough, John</name>
      </author>
      <author>
        <name>Snoeren, Alex C</name>
      </author>
    </item>
    <item>
      <title>Echidna: Programmable Schematics to Simplify PCB Design</title>
      <link>https://escholarship.org/uc/item/8wn4m97p</link>
      <description>In this paper we introduce Echidna, a hybrid schematic/ text-based language for describing PCB circuit schematics. Echidna allows designers to use high-level programming con- structs to describe schematics, supports modular, reusable design components with well-defined interfaces, and provides for complex parameterization of those modules. Echidna deeply integrates a high-level programming language into a schematic-based design flow. The designer can describe schematics in code, as a schematic, or as a seamless combination of the two. We demonstrate its usefulness with several case studies.&lt;p&gt;Pre-2018 CSE ID: CS2016-1017&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8wn4m97p</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Wang, Shengye</name>
      </author>
      <author>
        <name>Merrill, Devon</name>
      </author>
      <author>
        <name>Taylor, Chris</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>Signal Probability Based Statistical Timing Analysis</title>
      <link>https://escholarship.org/uc/item/8t4853vm</link>
      <description>We observe that Monte Carlo (SPICE) simulation provides the most
accurate and trustable statistical timing analysis, while the existing SSTA
method has completely ignored the effect of input statistics on chip timing
performance, and provides either accurate estimate nor pessimistic bound of the
actual chip timing performance statistics. We propose signal probability (i.e.,
the logic one occurrence probability for a signal) based statistical timing
analysis for improved accuracy and reduced pessimism over the existing SSTA
methods, and improved efficiency over Monte Carlo (SPICE) simulation. Our
experimental results show that our proposed SPSTA computes mean (standard
deviation) of signal arrival times within 6.2% (18.6%), while SSTA computes
mean (standard deviation) of signal arrival times within 13.40% (64.3%) of
Monte Carlo simulation results; SPSTA also provides signal probaiblity
estimation within 14.28% of Monte Carlo simulation results for the ISCAS'89
benchmark circuits.
&lt;p&gt;Pre-2018...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8t4853vm</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Liu, Bao</name>
      </author>
    </item>
    <item>
      <title>Analysis of Cross-layer Vulnerability to Variations: An Adaptive Instruction-level to Task-level Approach</title>
      <link>https://escholarship.org/uc/item/8m7737dh</link>
      <description>Variation in performance and power across manufactured parts and
their operating conditions is an accepted reality in aggressive CMOS processes.
This paper considers challenges and opportunities in identifying this variation
and methods to combat or even use these variations for improved computing
systems. We introduce the notion of instruction-level vulnerability (ILV) and
concurrent instruction reuse (CIR) to expose variation and its effects to the
software stack for use in architectural and runtime optimizations. Going
further up on the hardware-software stack, we also introduce the notion of
tasklevel vulnerability (TLV) as metadata to characterize dynamic variations.
In fact, TLV is a vertical abstraction that reflects manifestation of
circuit-level hardware variability in specific software context for parallel
execution model.&lt;p&gt;Pre-2018 CSE ID: CS2014-1004&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8m7737dh</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Rahimi, Abbas</name>
      </author>
      <author>
        <name>Benini, Luca</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Integrating Microsecond Circuit Switching into the Data Center</title>
      <link>https://escholarship.org/uc/item/8j85g8jn</link>
      <description>Recent proposals have employed optical circuit switching (OCS) to
reduce the cost of data center networks.  However, the relatively slow
switching times (10-100 ms) assumed by these approaches, and the accompanying
latencies of their control planes, has limited its use to only the largest data
center networks with highly aggregated and constrained workloads.  As faster
switch technologies become available, designing a control plane capable of
supporting them becomes a key challenge. In this paper, we design and implement
an OCS prototype capable of switching in 11.5 microseconds, and we use this
prototype to expose a set of challenges that arise when supporting switching at
microsecond time scales.  In response, we propose a microsecond-latency control
plane based on a circuit scheduling approach we call Traffic Matrix Scheduling
(TMS) that proactively communicates circuit assignments to communicating
entities so that circuit bandwidth can be used efficiently.&lt;p&gt;Pre-2018 CSE ID:...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8j85g8jn</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Porter, George</name>
      </author>
      <author>
        <name>Strong, Richard</name>
      </author>
      <author>
        <name>Farrington, Nathan</name>
      </author>
      <author>
        <name>Forencich, Alex</name>
      </author>
      <author>
        <name>Sun, Pang-Chen</name>
      </author>
      <author>
        <name>Rosing, Tajana Simunic</name>
      </author>
      <author>
        <name>Fainman, Yeshaiahu</name>
      </author>
      <author>
        <name>Papen, George</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
    </item>
    <item>
      <title>NetShare: Virtualizing Data Center Networks across Services</title>
      <link>https://escholarship.org/uc/item/8h1713t5</link>
      <description>Data centers lower costs by sharing the physical infrastructure
among multiple services.  However, the data center network should also ideally
provide bandwidth guarantees to each service in a tunable manner while
maintaining high utilization.  We describe {\em NetShare}, a new statistical
multiplexing mechanism for Data Center networks that does this without
requiring changes to existing routers.  NetShare allows the bisection bandwidth
of the network to be allocated across services based on simple weights
specified by a manager.  Bandwidth unused by a service is shared
proportionately by other services.  More precisely, NetShare provides weighted
hierarchical max-min fair sharing, a generalization of hierarchical fair
queuing of individual {\em links}.  We present three mechanisms to implement
NetShare including one that leverages TCP flows and requires no changes to
routers or servers.  We show experiments using multiple Hadoop instances and a
network of Fulcrum switches and...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8h1713t5</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Lam, Terry</name>
      </author>
      <author>
        <name>Radhakrishnan, Sivasankar</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
      <author>
        <name>Varghese, George</name>
      </author>
    </item>
    <item>
      <title>Programming Models for Sensor Networks: A Survey</title>
      <link>https://escholarship.org/uc/item/8fh2z68w</link>
      <description>Sensor networks have been used in various types of applications and
still have a huge potential. As an application logic becomes more complex,
growing number of people realize that programming sensor networks is difficult.
Part of the difficulty comes from their distributed nature, but the large
fraction is from other harsh situations they face such as unreliable
communication, faulty nodes, and extremely constrained resources. Researchers
have proposed different programming models to alleviate the difficulty, sharing
an ultimate goal of making programming easy while making full use of given
resources. In this paper, we first explore the requirements for programming
models for sensor networks. Then we present a taxonomy of the programming
models,  classified according to the level of abstractions they provide.  We
evaluate each work in terms of the requirements and discuss the  strategies how
the programming models strive to satisfy these requirements. Further, we
discuss some...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8fh2z68w</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Sugihara, Ryo</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>UbiSketch: Bringing Sketching out of the Closet</title>
      <link>https://escholarship.org/uc/item/8dp743qb</link>
      <description>As paper-based communication is being supplanted by digital channels
like E-mail, Facebook, and Flickr, so is handwritten and sketch-based
expression.  We posit that digital pen-and-paper technologies can bring the
unique affordances of paper-based communication to social media, providing new
channels of expression to those who favor handwriting and sketching.   We
present UbiSketch, a ubiquitous real-time sketch-based communication tool that
supports social communication using natural paper-based interaction.  UbiSketch
allows people to create drawings, doodles, and text notes with digital pens and
paper, and publish them via their mobile phones to online social networks or
e-mail.  In a 4-week user study, this novel modality successfully brought
sketching into the public realm, exhibiting characteristics of digital social
media such as rapid authoring and dissemination, while retaining sketching's
unique qualities of visual communication.  Friend responses to sketches were
more...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8dp743qb</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Cowan, Lisa</name>
      </author>
      <author>
        <name>Weibel, Nadir</name>
      </author>
      <author>
        <name>Pina, Laura R</name>
      </author>
      <author>
        <name>Hollan, James D</name>
      </author>
      <author>
        <name>Griswold, William G</name>
      </author>
    </item>
    <item>
      <title>Dynamic Deferral of Workload for Capacity Provisioning in Data Centers</title>
      <link>https://escholarship.org/uc/item/8bv2j2hp</link>
      <description>Recent increase in energy prices has led researchers to find better
ways for capacity provisioning in data centers to reduce energy wastage due to
the variation in workload. This paper explores the opportunity for cost saving
and proposes a novel approach for capacity provisioning under bounded latency
requirements for the workload. We investigate how many servers to be kept
active and how much workload to be delayed for energy saving while meeting
every deadline. We present an offline LP formulation for capacity provisioning
by dynamic deferral and give two online algorithms to determine the capacity of
the data center and the assignment of workload to servers dynamically. We prove
the feasibility of the online algorithms and show that their worst case
performance are bounded by a constant factor with respect to the offline
formulation. We validate our algorithms on synthetic workload generated from
two real HTTP traces and show that they actually perform much better in
practice...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8bv2j2hp</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Adnan, Muhammad Abdullah</name>
      </author>
      <author>
        <name>Ma, Yan</name>
      </author>
      <author>
        <name>Sugihara, Ryo</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Detecting Malicious Packet Losses</title>
      <link>https://escholarship.org/uc/item/899803r2</link>
      <description>In this paper we consider the problem of detecting whether a
compromised router is maliciously manipulating its stream of packets.  In
particular, we are concerned with a simple yet effective attack in which a
router selectively drops packets destined for some victim.  Unfortunately, it
is quite challenging to attribute a missing packet to a malicious action
because normal network congestion can produce the same effect.  Modern networks
routinely drop packets when the load temporarily exceeds a router's buffering
capacity.  Previous detection protocols have tried to address this problem
using a user-defined threshold: too many dropped packets implies malicious
intent.  However this heuristic is fundamentally unsound; setting this
threshold is, at best, an art and will necessarily create unnecessary false
positives or mask highly-focused attacks. We have designed, developed and
implemented a compromised router detection protocol that dynamically infers,
based on measured traffic...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/899803r2</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Mizrak, Alper T</name>
      </author>
      <author>
        <name>Marzullo, Keith</name>
      </author>
      <author>
        <name>Savage, Stefan</name>
      </author>
    </item>
    <item>
      <title>Algorithms for manifold learning</title>
      <link>https://escholarship.org/uc/item/8969r8tc</link>
      <description>Manifold learning is  a popular recent approach to nonlinear
dimensionality reduction.  Algorithms for this task are based on the idea that
the dimensionality of many data sets is only artificially high; though each
data point consists of perhaps thousands of features, it may be described as a
function of only a few underlying parameters. That is, the data points are
actually samples from a low-dimensional manifold that is embedded in a
high-dimensional space.   Manifold learning algorithms attempt to uncover these
parameters in order to find a low-dimensional representation of the data.  In
this paper, we discuss the motivation, background, and algorithms proposed for
manifold learning. Isomap, Locally Linear Embedding, Laplacian  Eigenmaps,
Semidefinite Embedding, and a host of variants of these algorithms are
examined.&lt;p&gt;Pre-2018 CSE ID: CS2008-0923&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/8969r8tc</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Cayton, Lawrence</name>
      </author>
    </item>
    <item>
      <title>Censorship-resistant Publishing</title>
      <link>https://escholarship.org/uc/item/86c1m73c</link>
      <description>As the web evolves, it is becoming easier to form communities based
on shared interests, and to create, publish, and query data on a wide variety
of topics. In order to fully deliver on the promise of free data exchange, any
community-supporting infrastructure needs to enforce the key requirement to
preserve privacy of the association of content providers with potential
sensitive published information. This privacy preserving publishing requirement
prevents censorship, harassment, or discrimination of users by third parties.
We propose a novel privacy-preserving distributed infrastructure in which data
resides only with the publishers owning it.  The infrastructure disseminates
user queries to publishers, who answer them at their own discretion.  The
infrastructure enforces a publisher k-anonymity guarantee, which  prevents
leakage of information about which publishers are capable of answering a
certain query. Given the virtual nature of the global data collection, we study
the...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/86c1m73c</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Curtmola, Emiran</name>
      </author>
      <author>
        <name>Deutsch, Alin</name>
      </author>
      <author>
        <name>Ramakrishnan, K. K.</name>
      </author>
      <author>
        <name>Srivastava, Divesh</name>
      </author>
    </item>
    <item>
      <title>An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks</title>
      <link>https://escholarship.org/uc/item/863626c7</link>
      <description>Wireless sensor nodes are increasingly being tasked with computation
and communication intensive functions while still subject to constraints
related to energy availability. On these embedded platforms, once all low power
design techniques have been explored, duty-cycling the various subsystems
remains the primary option to meet the energy and power constraints. This
requires the ability to provide spurts of high MIPS and high bandwidth
connections. However, due to the large overheads associated with duty-cycling
the computation and communication subsystems, existing high performance sensor
platforms are not efficient in supporting such an option. In this paper, we
present the design and optimizations taken in a gateway node that provides
access to a Wi-Fi radio in an on-demand basis. We discuss our strategies to
reduce duty-cycling related costs by partitioning the system and by reducing
the amount of time required to activate or deactivate the high-powered
components. We compare...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/863626c7</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Jin, Zhong-Yi</name>
      </author>
      <author>
        <name>Schurgers, Curt</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography</title>
      <link>https://escholarship.org/uc/item/82z8j1w8</link>
      <description>Double patterning lithography (DPL) is in current production for
memory products, and is widely viewed as inevitable for logic products at the
32nm node.  DPL decomposes and prints the shapes of a critical-layer layout in
two exposures.  In traditional single-exposure lithography, adjacent identical
layout features will have identical mean critical dimension (CD), and spatially
correlated CD variations.  However, with DPL, adjacent features can have
distinct mean CDs, and uncorrelated CD variations.  This introduces a new set
of 'bimodal' challenges for timing analysis and optimization. We assess the
potential impact of DPL on timing analysis error and guardbanding, and find
that the traditional `unimodal' characterization and analysis framework may not
be viable for DPL.  For example, using 45nm models, we find that different DPL
mask layout solutions can cause 50ps skew in clock distribution that is unseen
by traditional analyses. Different mask layouts can also result in 20\%...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/82z8j1w8</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Jeong, Kwangok</name>
      </author>
      <author>
        <name>Kahng, Andrew B</name>
      </author>
    </item>
    <item>
      <title>WikiAnalytics: Disambiguation of Keyword Search Results on Highly Heterogeneous Structured Data</title>
      <link>https://escholarship.org/uc/item/82f168vg</link>
      <description>Wikipedia infoboxes is an example of a seemingly structured, yet
extraordinarily heterogenous dataset, where any given record has only a tiny
fraction of all possible fields. Such data cannot be queried using traditional
means without a massive a priori integration effort, since even for a simple
request the result values span many record types and fields. On the other hand,
the solutions based on keyword search are too imprecise to exactly capture the
user's intent. To address these limitations, we propose WikiAnalytics system
that utilizes a novel search paradigm in order to derive tables of precise and
complete results from Wikipedia infobox records. The user starts with a keyword
search query that finds a superset of the result records, and then browses
clusters of records deciding which are and are not relevant. WikiAnalytics uses
three categories of clustering features based on record types, fields, and
values that matched the query keywords, respectively. Since the system...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/82f168vg</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Balmin, Andrey</name>
      </author>
      <author>
        <name>Curtmola, Emiran</name>
      </author>
    </item>
    <item>
      <title>ThemisMR: An I/O-Efficient MapReduce</title>
      <link>https://escholarship.org/uc/item/7zd7j8hp</link>
      <description>"Big Data" computing increasingly utilizes the MapReduce programming
model for scalable processing of large data collections. Many MapReduce jobs
are I/O-bound, and so minimizing the number of I/O operations is critical to
improving their performance. In this work, we present ThemisMR, a MapReduce
implementation that reads and writes data records to disk exactly twice, which
is the minimum amount possible for data sets that cannot fit in memory. In
order to minimize I/O, ThemisMR makes fundamentally different design decisions
from previous MapReduce implementations. ThemisMR performs a wide variety of
MapReduce jobs – including click log analysis, DNA read sequence alignment,
and PageRank – at nearly the speed of TritonSort’s record-setting sort
performance.&lt;p&gt;Pre-2018 CSE ID: CS2012-0983&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7zd7j8hp</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Rasmussen, Alexander</name>
      </author>
      <author>
        <name>Conley, Michael</name>
      </author>
      <author>
        <name>Kapoor, Rishi</name>
      </author>
      <author>
        <name>Lam, Vinh The</name>
      </author>
      <author>
        <name>Porter, George</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
    </item>
    <item>
      <title>Recognizing Groceries in situ Using in vitro Training Data</title>
      <link>https://escholarship.org/uc/item/7w80w06s</link>
      <description>The problem of using pictures of objects captured under ideal
imaging conditions (here referred to as in vitro) to recognize objects in
natural environments (in situ) is an emerging area of interest in computer
vision and pattern recognition. Examples of tasks in this vein include
assistive vision systems for the blind and object recognition for mobile
robots; the proliferation of image databases on the web is bound to lead to
more examples in the near future. Despite its importance, there is still a need
for a freely available database to facilitate study of this kind of
training/testing dichotomy. In this work one of our contributions is a new
multimedia database of 120 grocery products, GroZi-120. For every product, two
different recordings are available: in vitro images extracted from online
grocery websites, and in situ images extracted from camcorder video collected
inside a grocery store. As an additional contribution, we present the results
of applying three commonly used...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7w80w06s</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Merler, Michele</name>
      </author>
      <author>
        <name>Galleguillos, Carolina</name>
      </author>
      <author>
        <name>Belongie, Serge</name>
      </author>
    </item>
    <item>
      <title>SAFE: Fast, Verifiable Sanitization for SSDs</title>
      <link>https://escholarship.org/uc/item/7s6184dq</link>
      <description>We propose a hybrid approach to sanitizing SSDs that combines speed
of cryptographic key destruction with the verifiability of explicitly erasing
the storage media. The technique, called Scramble and Finally Erase (SAFE),
stores encrypted data in the drive and uses a two step process for
sanitization. First, it destroys the key. Then, SAFE erases every physical page
in the SSD. After this step, verification is a simple matter of dismantling the
drive and verifying that the flash chips are actually erased.&lt;p&gt;Pre-2018 CSE ID: CS2011-0963&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7s6184dq</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Swanson, Steven</name>
      </author>
      <author>
        <name>Wei, Michael</name>
      </author>
    </item>
    <item>
      <title>Quasi-ASICs: Trading Area for Energy by Exploiting Similarity in Synthesized Cores for Irregular Code</title>
      <link>https://escholarship.org/uc/item/7nz0178r</link>
      <description>The transistor density continues to increase exponentially, but the
power dissipation per transistor improves only slightly with each generation of
Moore’s law. Given the constant chip-level power budgets, this exponentially
decreases the fraction of the transistors that can be active simultaneously
with each technology generation. Hence, while the area budget continues to
increase exponentially, the power budget has become a first-order design
constraint in current processors. In this regime, utilizing transistors to
design specialized cores that optimize energy-per-computation becomes an
effective approach to improve the system performance. To trade transistors for
energy efficiency in a scalable manner, we propose quasi application-specific
integrated circuits, or QASICs, specialized processors capable of executing
multiple general- purpose applications while providing an order-of-magnitude
more energy efficiency than a general-purpose processor. The QASIC design flow
is based...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7nz0178r</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Venkatesh, Ganesh</name>
      </author>
      <author>
        <name>Sampson, Jack</name>
      </author>
      <author>
        <name>Goulding, Nathan</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
      <author>
        <name>Taylor, Michael</name>
      </author>
    </item>
    <item>
      <title>A general agnostic active learning algorithm</title>
      <link>https://escholarship.org/uc/item/7jn4f274</link>
      <description>We present a simple, agnostic active learning algorithm that works
for any hypothesis class of bounded VC dimension, and any data distribution.
Our algorithm extends a scheme of Cohn, Atlas, and Ladner to the agnostic
setting, by (1) reformulating it using a reduction to supervised learning and
(2) showing how to apply generalization bounds even for the non-i.i.d. samples
that result from selective sampling. We provide a general characterization of
the label complexity of our algorithm. This quantity is never more than the
usual PAC sample complexity of supervised learning, and is exponentially
smaller for some hypothesis classes and distributions. We also demonstrate
improvements experimentally.&lt;p&gt;Pre-2018 CSE ID: CS2007-0898&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7jn4f274</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Dasgupta, Sanjoy</name>
      </author>
      <author>
        <name>Hsu, Daniel</name>
      </author>
      <author>
        <name>Monteleoni, Claire</name>
      </author>
    </item>
    <item>
      <title>Predicting Performance Across Compilations</title>
      <link>https://escholarship.org/uc/item/7j213325</link>
      <description>Performance comparisons are ubiquitous in computer science. The
proceedings of most conferences are filled with bar charts comparing the
performance of some computer system to another. For example, computer
architects compare the performance of processors, and compiler writers compare
the performance of generated code. It is difficult to prove that one computer
system is always faster than another for all possible workloads, so these
performance comparisons are used as predictors: performance is compared on
several representative workloads, and the results are used to argue that one
computer system is generally faster than another. Unfortunately, there are many
scenarios where it is difficult to make a fair performance comparison. This
dissertation focuses on two such scenarios. The first scenario involves
simulations in computer architecture. Computer architects typically evaluate
new processor designs through slow cycle-level simulation. Because of the poor
performance of cycle-level...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7j213325</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Lau, Jeremy</name>
      </author>
    </item>
    <item>
      <title>Characterizing Flash Memory: Anomalies, Observations, and Applications</title>
      <link>https://escholarship.org/uc/item/7hf8346g</link>
      <description>Despite ﬂash memory’s promise, it suffers from many
idiosyncrasies such as limited durability, data integrity problems, and
asymmetry in operation granularity. As architects, we aim to ﬁnd ways to
overcome these idiosyncrasies while exploiting ﬂash memory’s useful
characteristics. To be successful, we must understand the trade-offs between
the performance, cost (in both power and dollars), and reliability of ﬂash
memory. In addition, we must understand how different usage patterns affect
these characteristics. Flash manufacturers provide only vague guidelines about
these metrics, and this lack of detail makes it difﬁcult to design systems
that fully exploit ﬂash memory’s capabilities. We have empirically
characterized ﬂash memory technology from ﬁve manufacturers by directly
measuring the performance, power, and reliability. We demonstrate that
performance varies signiﬁcantly between vendors, devices, and from the
data-sheet. We also demonstrate and quantify some unexpected device
characteristics...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7hf8346g</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Grupp, Laura</name>
      </author>
      <author>
        <name>Caulfield, Adrian</name>
      </author>
      <author>
        <name>Coburn, Joel</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
      <author>
        <name>Yaakobi, Eitan</name>
      </author>
      <author>
        <name>Siegel, Paul</name>
      </author>
    </item>
    <item>
      <title>DieCast: Testing Distributed Systems with an Accurate Scale Model</title>
      <link>https://escholarship.org/uc/item/7ct9w971</link>
      <description>Large-scale network services can consist of tens of thousands of
machines running thousands of unique software configurations spread across
hundreds of physical networks.  Testing such services for complex performance
problems, configuration errors, and fault tolerance remains a difficult
problem. Existing testing techniques, for example through simulation or running
smaller instances of a service, have limitations in predicting overall service
behavior. Although technically and economically infeasible at this time,
testing should ideally be performed at the same scale and with the same
configuration as the deployed service.  We present DieCast, an approach to
scaling network services; we multiplex all of the nodes in a given service
configuration as virtual machines (VM) spread across a much smaller number of
physical machines in a test harness. CPU, network, and disk are then accurately
scaled to provide the illusion that each VM matches a machine from the original
service in...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7ct9w971</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Gupta, Diwaker</name>
      </author>
      <author>
        <name>Vishwanath, Kashi</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
    </item>
    <item>
      <title>Neon: System Support for Derived Data Management</title>
      <link>https://escholarship.org/uc/item/7c87654g</link>
      <description>Modern organizations face increasingly complex information
management requirements. A combination of commercial needs, legal liability and
regulatory imperatives has created a patch-work of mandated policies.  Among
these, personally identifying customer records must be carefully
access-controlled, sensitive files must be encrypted on mobile computers to
guard against physical theft and intellectual property must be protected from
both exposure and ``poisoning.''  However, enforcing such policies can be quite
difficult in practice since users routinely share data over networks and derive
new files from these inputs -- incidentally laundering any policy restrictions.
In this paper, we describe a VMM system called Neon that transparently labels
derived data using byte-level ``tints'' and tracks these labels end-to-end
across commodity applications, operating systems and networks.  We demonstrate
that this mechanism allows the enforcement of a variety of data management
policies,...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7c87654g</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Zhang, Qing</name>
      </author>
      <author>
        <name>McCullough, John</name>
      </author>
      <author>
        <name>Ma, Justin</name>
      </author>
      <author>
        <name>Schear, Nabil</name>
      </author>
      <author>
        <name>Vrable, Michael</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
      <author>
        <name>Snoeren, Alex C</name>
      </author>
      <author>
        <name>Voelker, Geoffrey M</name>
      </author>
      <author>
        <name>Savage, Stefan</name>
      </author>
    </item>
    <item>
      <title>SleepServer: Energy Savings for Enterprise PCs by Allowing them to
Sleep</title>
      <link>https://escholarship.org/uc/item/77b8c38f</link>
      <description>Energy consumption of IT equipment is significant in enterprises.
While low power sleep modes have existed for some time, their use in
wall-powered desktop PCs is not prevalent due to the requirement of maintaining
network presence and availability for network facing applications. In this
paper, we describe the architecture and implementation of SleepServer, a system
that enables hosts to transition to low-power sleep states while keeping them
reachable at the highest layers of the network and software stack. SleepServer
works across heterogeneous computing environments and hierarchical multi-domain
networks. SleepServer requires no changes to the underlying networking
infrastructure or any additional hardware on the end hosts, requiring only
simple software agents to be installed. We detail results from our experience
in deploying SleepServer in a medium scale enterprise with a sample set of
thirty machines that were instrumented to provide accurate real-time
measurements of...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/77b8c38f</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Agarwal, Yuvraj</name>
      </author>
      <author>
        <name>Savage, Stefan</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Estimating Profitability of Alternative Crypto-currencies</title>
      <link>https://escholarship.org/uc/item/7682n2h8</link>
      <description>Digital currencies have flourished in recent years, buoyed by the tremendous success of Bitcoin. These blockchain-based currencies, called altcoins, have attracted enthusiasts who enter the market by mining or buying them. To mine or to buy, however, can be a difficult decision; each altcoin is different from another, and the market tends to be volatile. In this work, we analyze the profitability of mining and speculation for 36 altcoins using real-world blockchain and trade data. Using opportunity cost as a metric, we estimate the mining cost for a coin with respect to a more popular coin. For every dollar invested in mining or buying a coin, we also estimate the revenue under various conditions, such as time of market entry and hold positions. While some coins offer the potential for spectacular returns, many follow a simple bubble-and-crash scenario, which highlights the extreme risks---and potential gains---in altcoin markets.&lt;p&gt;Pre-2018 CSE ID: CS2017-1019&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/7682n2h8</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Huang, Danny Yuxing</name>
      </author>
      <author>
        <name>Levchenko, Kirill</name>
      </author>
      <author>
        <name>Snoeren, Alex C</name>
      </author>
    </item>
    <item>
      <title>Improved Distributed Simulation of Sensor Networks based on Sensor Node Sleep Time</title>
      <link>https://escholarship.org/uc/item/73f2501s</link>
      <description>Sensor network simulators are important tools for the design,
implementation and evaluation of wireless sensor networks. Due to the large
computational requirements necessary for simulating wireless sensor networks
with high fidelity, many wireless sensor network simulators, especially the
cycle accurate ones, employ distributed simulation techniques to leverage the
combined resources of multiple processors or computers. However, the large
overheads in synchronizing sensor nodes during distributed simulations of
sensor networks result in a significant increase in simulation time. In this
paper, we present a novel technique that could significantly reduce such
overheads by minimizing the number of sensor node synchronizations during
simulations. We implement this technique in Avrora, a widely used parallel
sensor network simulator, and achieve a speedup of up to 11 times in terms of
average simulation speed in our test cases. For applications that have lower
duty cycles, the speedups...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/73f2501s</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Jin, Zhong-Yi</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Fast structural metric learning</title>
      <link>https://escholarship.org/uc/item/72t332tp</link>
      <description>We develop an efficient optimization procedure for learning linear
transformations of data to produce structured outputs, e.g., nearest-neighbor
rankings or connectivity graphs induced by distance.  The proposed method
solves a semi-definite programming problem by reducing to a sequence of small
quadratic programs,  resulting in significant reductions in training
complexity. Experiments demonstrate that the proposed method is robust,
efficient, and outperforms alternative methods in high-noise settings.&lt;p&gt;Pre-2018 CSE ID: CS2012-0979&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/72t332tp</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Mcfee, Brian</name>
      </author>
      <author>
        <name>Lanckriet, Gert</name>
      </author>
    </item>
    <item>
      <title>Temporal Memoization for Energy-Efficient Timing Error Recovery in GPGPU Architectures</title>
      <link>https://escholarship.org/uc/item/72p4n0b4</link>
      <description>Manufacturing and environmental variability lead to timing errors in
computing systems that are typically corrected by error detection and
correction mechanisms at the circuit level. The cost and speed of recovery can
be improved by memoization-based optimization methods that exploit spatial or
temporal parallelisms in suitable computing fabrics such as general-purpose
graphics processing units (GPGPUs). We propose here a temporal memoization
technique for use in floating-point units (FPUs) in GPGPUs that uses value
locality inside data-parallel programs. The technique recalls (memorizes) the
context of error-free execution of an instruction on a FPU. Therefore, it
avoids redundant execution and saves energy for FPU. To enable scalable and
independent recovery, a single-cycle lookup table (LUT) is tightly coupled to
every FPU to maintain contexts of recent error-free executions. The LUT reuses
these memorized contexts to exactly, or approximately, correct errant FP
instructions...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/72p4n0b4</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Rahimi, Abbas</name>
      </author>
      <author>
        <name>Benini, Luca</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Does Image Segmentation Improve Object Categorization?</title>
      <link>https://escholarship.org/uc/item/70s1n7n9</link>
      <description>Image segmentation and object recognition are among the most
fundamental problems in computer vision, and the potential interaction between
these tasks has been discussed for many years. The usefulness of recognition
for segmentation has been demonstrated with various top-down segmentation
algorithms, however, the impact of bottom-up image segmentation as
pre-processing for object recognition is not well understood. One factor
impeding the utility of segmentation for recognition is the unsatisfactory
quality of image segmentation algorithms. In this work we take advantage of a
recently proposed method for computing multiple stable segmentations and
illustrate the application of bottom-up image segmentation as a preprocessing
step for object recognition and categorization. We extend a popular
bag-of-features recognition model to provide multiple class categorization and
localization of objects in images. We compare our categorization results to
that of a conventional bag-of-features...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/70s1n7n9</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Rabinovich, Andrew</name>
      </author>
      <author>
        <name>Vedaldi, Andrea</name>
      </author>
      <author>
        <name>Belongie, Serge</name>
      </author>
    </item>
    <item>
      <title>A Practical Microcylinder Appearance Model for Cloth Rendering</title>
      <link>https://escholarship.org/uc/item/6v11p5b0</link>
      <description>This paper introduces a simple shading model for cloth. The model
can simulate both the anisotropic highlights on cloth as well as the complex
color shifts seen in cloth made of different colored threads. Our model is
based on extensive Bidirectional Reflectance Distribution Function (BRDF)
measurements of several cloth samples. We have also measured the scattering
profile of several different individual cloth threads. Based on these
measurements we have derived a simple model capable of predicting the light
scattered by different threads. We model cloth as a collection of threads in a
weave pattern which provides information about the coverage of the different
thread types as well as their tangent directions. Our model also accounts for
shadowing and masking by the threads. We validate our model by comparing
predicted and measured values and we show how we can use the model to recover
parameters for different cloth samples including silk, velvet, linen, and
polyester with varying...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6v11p5b0</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Sadhegi, Iman</name>
      </author>
      <author>
        <name>Bisker, Oleg</name>
      </author>
      <author>
        <name>De Deken, Joachim</name>
      </author>
      <author>
        <name>Wann Jensen, Henrik</name>
      </author>
    </item>
    <item>
      <title>Battery Provisioning and Associated Costs for Data Center Power Capping</title>
      <link>https://escholarship.org/uc/item/6tt9z3n5</link>
      <description>Power over-subscription can reduce costs for modern data centers.
However, designing the power infrastructure for a lower operating power point
than the aggregated peak power of all servers requires dynamic techniques to
avoid high peak power costs and, even worse, tripping circuit breakers. This
work presents an architecture for distributed per-server UPSs that stores
energy during low activity periods and uses this energy during power spikes.
This work advocates explicit sizing of the distributed UPS batteries for power
capping and provides a methodology to properly select the properties of the
battery in order to reduce total datacenter cost of ownership per server.
Depending on workload diurnal patterns and oversubscription assumption this
approach can achieve up 5-10% reduction in overall costs per server.&lt;p&gt;Pre-2018 CSE ID: CS2012-0985&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6tt9z3n5</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Kontorinis, Vasileios</name>
      </author>
      <author>
        <name>Sampson, Jack</name>
      </author>
      <author>
        <name>Zhang, Liuyi Eric</name>
      </author>
      <author>
        <name>Akslani, Baris</name>
      </author>
      <author>
        <name>Homayoun, Houman</name>
      </author>
      <author>
        <name>Rosing, Tajana Simunic</name>
      </author>
      <author>
        <name>Tullsen, Dean</name>
      </author>
    </item>
    <item>
      <title>Dahu: Improved Data Center Multipath Forwarding</title>
      <link>https://escholarship.org/uc/item/6ps421k5</link>
      <description>Solving "Big Data" problems requires bridging massive quantities of
compute, memory, and storage, which requires significant amounts of bisection
bandwidth. Topologies like Fat-tree, VL2, and HyperX achieve a scale-out design
by leveraging multiple paths from source to destination. However, traditional
routing protocols are not able to effectively utilize these links while also
harnessing spare network capacity to better statistically multiplex network
resources. In this work we present Dahu, a switch mechanism for efficiently
load balancing traffic in multipath networks. Dahu avoids congestion hot-spots
by dynamically spreading traffic uniformly across links, and forwarding traffic
over non-minimal paths where possible. By performing load balancing primarily
using local information, Dahu can act more quickly than centralized approaches,
and responds to failure gracefully. Our evaluation shows that Dahu delivers up
to 50% higher throughput relative to ECMP in an 8,192 server Fat-tree...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6ps421k5</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Radhakrishnan, Sivasankar</name>
      </author>
      <author>
        <name>Kapoor, Rishi</name>
      </author>
      <author>
        <name>Tewari, Malveeka</name>
      </author>
      <author>
        <name>Porter, George</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
    </item>
    <item>
      <title>Censorship-resistant Publishing</title>
      <link>https://escholarship.org/uc/item/6pg8f6vh</link>
      <description>As the web evolves, it is becoming easier to form communities based
on shared interests, and to create and publish data on a wide variety of
topics. With this "democratization of information creation" comes the natural
desire to make one's data accessible for querying within the community and also
be able to query the global collection that is the union of all local data
collections of others within the community. In order to fully deliver on the
promise of free data exchange, any community-supporting infrastructure needs to
enforce the key requirement of being resistant to censorship by third parties,
be they of governmental, corporate, of other special interest nature.
Censorship resistance precludes some obvious approaches that reuse and build on
existing centralized technologies, e.g., search engines, hosted online
communities, etc. We propose a distributed infrastructure in which data resides
only with the publishers owning it.  The infrastructure disseminates user
queries...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6pg8f6vh</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Curtmola, Emiran</name>
      </author>
      <author>
        <name>Deutsch, Alin</name>
      </author>
      <author>
        <name>Ramakrishnan, K. K.</name>
      </author>
      <author>
        <name>Srivastava, Divesh</name>
      </author>
    </item>
    <item>
      <title>An Efficient FPGA Implementation of Scalable Matrix Inversion Core using QR Decomposition</title>
      <link>https://escholarship.org/uc/item/6mj094vk</link>
      <description>We present a novel scalable architecture for matrix inversion that
uses the modified Gram-Schmidt algorithm based on QR decomposition. Our core
achieves a throughput of 0.18M updates per second for a 4 x 4 matrix using 19
bits of precision on a Xilinx Virtex4 SX FPGA. We also present two different
designs which use longer data lines, 26 and 32 bits, and compare our results
with another matrix inversion architecture which is the only scalable approach
so far. We show that our core is significantly faster than the other published
FPGA implementation as it requires fewer resources due to the usage of fixed
point arithmetic and an effective resource utilization. We show that our
proposed architecture is scalable by presenting the results for 6 x 6 and 8 x 8
matrices.&lt;p&gt;Pre-2018 CSE ID: CS2009-0938&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6mj094vk</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Irturk, Ali</name>
      </author>
      <author>
        <name>Mirzaei, Shahnam</name>
      </author>
      <author>
        <name>Kastner, Ryan</name>
      </author>
    </item>
    <item>
      <title>Simulations of Wireless Sensor Networks: A Survey</title>
      <link>https://escholarship.org/uc/item/6mc0v607</link>
      <description>Simulators are important tools for the design, implementation and
evaluation of sensor networks and have been the subject of intense research in
the past decade. The resource constrained nature of sensor platforms as well as
the unique working environments and deployment scenarios of sensor networks
give special requirements and challenges to simulator design. More than 20
simulators have been developed for sensor networks by various research groups
to address different problems and needs. In this paper, we first explore the
requirements for a modern sensor network simulator. Then we study simulation
techniques and classify existing sensor network simulators according to their
architectures, designs and levels of abstractions. Finally, we discuss the
future research directions of wireless sensor network simulators.&lt;p&gt;Pre-2018 CSE ID: CS2008-0925&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6mc0v607</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Jin, Zhong-Yi</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Suspending and Resuming Network Applications using Session Continuations</title>
      <link>https://escholarship.org/uc/item/6km5s82h</link>
      <description>Migrate is a system service that allows network applications to
suspend upon disconnection and properly resume when connectivity is restored.
Migrate uses session continuations, which allow applications to explicitly
record all the state and resources required to correctly resume. Migrate
virtualizes network connections to function across network address changes,
allows portions of an application to be suspended and securely resumed, and
optimizes scarce system resources on servers handling many suspended clients.
We demonstrate that the continuation abstraction is both useful and efﬁcient
by showing how two important applications, SSH and Icecast, can use Migrate to
implement a suspend/resume feature. We ﬁnd that the required source code
changes are between 0.5% and 1.75% of the total, that the generated
continuations are between 1% and 5% of the memory footprint of the entire
process, and that session resumption times are small (a few hundred
milliseconds) compared to typical...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6km5s82h</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Snoeren, Alex C</name>
      </author>
      <author>
        <name>Panigrahi, Debashis</name>
      </author>
      <author>
        <name>Mukhopadhyay, Shoubhik</name>
      </author>
      <author>
        <name>Balakrishnan, Hari</name>
      </author>
      <author>
        <name>Kaashoek, M. Frans</name>
      </author>
    </item>
    <item>
      <title>Querying Data Sources That Export Infinite Sets of Views</title>
      <link>https://escholarship.org/uc/item/6gs6z92r</link>
      <description>We study the problem of querying data sources that accept only a
limited set of queries, such as sources accessible by Web services which can
implement very large (potentially infinite) families of queries. We revisit a
classical setting in which the application queries are conjunctive queries and
the source accepts families of (possibly parameterized) conjunctive queries
specified as the expansions of a (potentially recursive) Datalog program with
parameters.  We say that query Q is expressible by the program P if it is
equivalent to some expansion of P. Q is supported by P if it has an equivalent
rewriting using some finite set of P's expansions.  We present the first study
of expressibility and support for sources that satisfy integrity constraints,
which is generally the case in practice. We start by closing a problem left
open by prior work even while ignoring constraints, namely the precise
relationship between expressibility and support: surprisingly, we show them to
be...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6gs6z92r</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Cautis, Bogdan</name>
      </author>
      <author>
        <name>Deutsch, Alin</name>
      </author>
      <author>
        <name>Onose, Nicola</name>
      </author>
    </item>
    <item>
      <title>CACTI-IO Technical Report</title>
      <link>https://escholarship.org/uc/item/6f6904sc</link>
      <description>We describe CACTI-IO, an extension to CACTI that includes power,
area and timing models for the IO and PHY of the off-chip memory interface for
various server and mobile configurations. CACTI-IO enables quick design space
exploration of the off-chip IO along with the DRAM and cache parameters. We
describe the models added to CACTI-IO that help include the off-chip impact to
the tradeoffs between memory capacity, bandwidth and power. This technical
report also provides three standard configurations  for the input parameters
(DDR3, LPDDR2 and Wide-IO) and illustrates how the models can be modified for a
custom configuration. The models are validated against SPICE simulations and
show that we are within 0-15% error for different configurations. We also
compare with measured results.&lt;p&gt;Pre-2018 CSE ID: CS2012-0986&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6f6904sc</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Jouppi, Norman</name>
      </author>
      <author>
        <name>Kahng, Andrew</name>
      </author>
      <author>
        <name>Muralimanohar, Naveen</name>
      </author>
      <author>
        <name>Srinivas, Vaishnav</name>
      </author>
    </item>
    <item>
      <title>Flame: Efficient and Robust Hardware Load Balancing Flame: Efficient and Robust Hardware Load Balancing for Data Center Routers</title>
      <link>https://escholarship.org/uc/item/6cq720mg</link>
      <description>As single TCP flows approach 10 Gbps, static hash ECMP load
balancing — used by routers today– does a poor job of balancing load in
data centers. We describe a new load balancing algorithm, Flame, that is
implementable at 480 Gbps with small memory and uses two novel mechanisms.
First, Flame uses a Discounting Rate Estimator (DRE); unlike exponential
averaging, DRE quickly measures bursts and yet retains memory of recent bursts.
Second, Flame binds flows to hash functions and not to paths. We show Flame is
more resilient and efficient than the earlier Flare scheme, and provides better
load balancing and is more deployable than Hedera. Flame also allows
rebalancing of flows in hardware at rapid rates. This is interesting because we
show TCP experiments at 1 and 10 Gbps that demonstrate that recent Linux stacks
after 2.6.14 can tolerate rebalancing once every 10 packets with negligible
loss of throughput. On the other hand, Windows 2008 stacks have degraded TCP
throughput if rebalancing...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6cq720mg</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Edsall, Tom</name>
      </author>
      <author>
        <name>Fingerhut, Andy</name>
      </author>
      <author>
        <name>Lam, Terry</name>
      </author>
      <author>
        <name>Pan, Rong</name>
      </author>
      <author>
        <name>Varghese, George</name>
      </author>
    </item>
    <item>
      <title>Multiple Instance Learning with Query Bags</title>
      <link>https://escholarship.org/uc/item/6c4778j8</link>
      <description>In many machine learning applications, precisely labeled data is
either burdensome or impossible to collect. Multiple Instance Learning (MIL),
in which training data is provided in the form of labeled bags rather than
labeled instances, is one approach for dealing with ambiguously labeled data.
In this paper we argue that in many applications of MIL (e.g. image, audio,
text, bioinformatics) a single bag actually consists of a large or infinite
number of instances, such as all points on a low dimensional manifold.  For
practical reasons, these bags get subsampled before training.  Instead, we
introduce a MIL formulation which directly models the underlying structure of
these bags.  We propose and analyze the query bag model, in which instances are
obtained by repeatedly querying an oracle in a way that can capture
relationships between instances.  We show that sampling more instances results
in better classification performance, which motivates us to develop algorithmic
strategies...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6c4778j8</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Babenko, Boris</name>
      </author>
      <author>
        <name>Dollar, Piotr</name>
      </author>
      <author>
        <name>Belongie, Serge</name>
      </author>
    </item>
    <item>
      <title>Data Mule Scheduling in Sensor Networks: Scheduling under Location and Time Constraints</title>
      <link>https://escholarship.org/uc/item/69g3t3hg</link>
      <description>Unlike multi-hop forwarding, an alternative and relatively new
approach for efficient data collection in sensor networks is to exploit the
mobility. Particularly, we consider collecting data from static sensor nodes
using a “data mule” via wireless communication. A data mule is a mobile
node that has wireless communication capability and also a sufficient amount of
storage to store the data from the sensors in the field. A data mule travels
across the sensing field and collects data from each sensor node when the
distance is short, and later deposits all the data to the base station. In this
way, each sensor node can conserve a significant amount of energy, since it
only needs to send the data over a shorter distance and has no need to forward
other sensors’ data all the way to the base station. In this paper, we are
interested in the following problem: “how to control a data mule such that it
collects data from all the nodes in the minimal amount of time”. We call it
the data...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/69g3t3hg</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Sugihara, Ryo</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Optimizing Energy-Latency Trade-off in Sensor Networks with Controlled Mobility</title>
      <link>https://escholarship.org/uc/item/67p7k1pr</link>
      <description>We consider the problem of planning path and speed of a “data
mule” in a sensor network. This problem is encountered in various situations,
such as modeling the motion of a data-collecting UAV in a field of sensors for
structural health monitoring. Our specific context here is use of a data mule
as an alternative or supplement to multihop forwarding in a sensor network.
While a data mule can reduce the energy consumption at each sensor node, it
increases the latency from the time the data is generated at a node to the time
the base station receives it. In this paper, we introduce the “data mule
scheduling” or DMS framework that enables data mule motion planning to
minimize the data delivery latency. The DMS framework is general; it can
express many previously proposed problem formulations and problem settings
related to data mules. We design algorithms for DMS and extend to the more
general case of combined data mule and multihop forwarding to enable a flexible
trade-off between...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/67p7k1pr</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Sugihara, Ryo</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Improving VNC Performance</title>
      <link>https://escholarship.org/uc/item/6325p8bz</link>
      <description>Virtual Network Computing, or VNC, is a popular thin client
application used to access files and applications on remote computers.  It is
especially relevant as infrastructure to support ubiquitous computing
applications, as it offers a way to run data-and-computation-intensive
applications and allow users to access them through lightweight devices.
However, VNC can suffer from significant losses in throughput when there is
high latency between the client and server.  In this work, we present a Message
Accelerator proxy for VNC.  This Message Accelerator mitigates high latency
network effects while maintaining the advantages of a client-pull system.  By
operating near/on the server, it can send updates to the client at a rate
corresponding to proxy-server interactions which are faster than client-server
interactions. When testing using video, our Message Accelerator design results
in frame rates an order of magnitude higher than plain VNC when running under
high latency conditions.&lt;p&gt;Pre-2018...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/6325p8bz</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Taylor, Cynthia</name>
      </author>
      <author>
        <name>Pasquale, Joseph</name>
      </author>
    </item>
    <item>
      <title>Learning to Traverse Image Manifolds</title>
      <link>https://escholarship.org/uc/item/62f8k8cq</link>
      <description>We present a new algorithm, Locally Smooth Manifold Learning (LSML),
that learns a warping function from a point on an manifold to its neighbors.
Important characteristics of LSML include the ability to recover the structure
of the manifold in sparsely populated regions and beyond the support of the
provided data.  Applications of our proposed technique include embedding with a
natural out-of-sample extension and tasks such as tangent distance estimation,
frame rate up-conversion, video compression and motion transfer.&lt;p&gt;Pre-2018 CSE ID: CS2007-0876&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/62f8k8cq</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Dollar, Piotr</name>
      </author>
      <author>
        <name>Rabaud, Vincent</name>
      </author>
      <author>
        <name>Belongie, Serge</name>
      </author>
    </item>
    <item>
      <title>Can You Infect Me Now? A Treatise on the Propagation of Malware in a Cellular Phone Network</title>
      <link>https://escholarship.org/uc/item/5w9600dd</link>
      <description>The prolific spread of mobile phones through all corners of the
globe has only been matched by their rapid increase in computing power.  As
cellular phones become further integrated into the fabric of everyday life,
their value to attackers will rise accordingly.  As a result, the widespread
debilitating outbreak of self-propagating malware in the cell phone environment
is a matter of "when", rather than "if." Although self-propagating malware is
well understood in the Internet, mobile phone networks have very different
characteristics in terms of topologies, services, provisioning and capacity,
devices, and communication patterns.  To understand the propagation of malware
in this new environment, we have developed an event-driver simulator that
captures the characteristics and constraints of mobile phone networks. Key
elements of the simulator are a network topology generator (RACoON), which
creates realistic topologies and provisioned capacities of the network
infrastructure,...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/5w9600dd</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Fleizach, Chris</name>
      </author>
    </item>
    <item>
      <title>Trajectory and Policy Aware Sender Anonymity in Location Based Services</title>
      <link>https://escholarship.org/uc/item/5kp9f7cq</link>
      <description>We consider Location-based Service (LBS) settings, where a LBS
provider logs the requests sent by mobile device users over a period of time
and later wants to publish/share these logs. Log sharing can be extremely
valuable for advertising, data mining research and network management, but it
poses a serious threat to the privacy of LBS users. Sender anonymity solutions
prevent a malicious attacker from inferring the interests of LBS users by
associating them with their service requests after gaining access to the
anonymized logs. With the fast-increasing adoption of smartphones and the
concern that historic user trajectories are becoming more accessible, it
becomes necessary for any sender anonymity solution to protect against
attackers that are trajectory-aware (i.e. have access to historic user
trajectories) as well as policy-aware (i.e they know the log anonymization
policy). We call such attackers TP-aware. This paper introduces a first privacy
guarantee against TP-aware attackers,...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/5kp9f7cq</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Deutsch, Alin</name>
      </author>
      <author>
        <name>Hull, Richard</name>
      </author>
      <author>
        <name>Vyas, Avinash</name>
      </author>
      <author>
        <name>Keliang Zhao, Kevin</name>
      </author>
    </item>
    <item>
      <title>ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration</title>
      <link>https://escholarship.org/uc/item/5jd3c1gv</link>
      <description>As industry moves towards many-core chips, networks-on-chip (NoCs)
are emerging as the scalable fabric for interconnecting the cores. With power
now the first-order design constraint, early-stage estimation of NoC power has
become crucially important.  ORION was amongst the first NoC power models
released, and has since been fairly widely used for early-stage power
estimation of NoCs. However, when validated against recent NoC prototypes –
the Intel 80-core Teraflops chip and the Intel Scalable Communications Core
(SCC) chip – we saw significant deviation that can lead to erroneous NoC
design choices. This prompted our development of ORION 2.0, an extensive
enhancement of the original ORION models which includes completely new
subcomponent power models, area models, as well as improved and updated
technology models. Validating against the two Intel chips saw ORION 2.0
bringing a substantial improvement in accuracy over the original ORION. A case
study with these power models plugged...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/5jd3c1gv</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Kahng, Andrew</name>
      </author>
      <author>
        <name>Li, Bin</name>
      </author>
      <author>
        <name>Peh, Li-Shiuan</name>
      </author>
      <author>
        <name>Samadi, Kambiz</name>
      </author>
    </item>
    <item>
      <title>p-ray: a Parallelization Analysis Tool for Multicore Software</title>
      <link>https://escholarship.org/uc/item/5gk6v3fx</link>
      <description>In this paper, we propose a novel set of techniques that allows
multicore programmers and architects alike to rapidly estimate the availability
of parallelism in their target programs. We present p-ray, which, given an
application and the input, shows the nested relationship and availability of
parallelism across different regions in complex programs, using a parallelism
chart, or p-chart. P-ray also prioritizes the regions, suggesting the ordering
that the programmer should attack them in, based on the estimated parallelism
and the code complexity. P-ray can also estimate the kind of parallelism (TLP,
DLP or ILP) that is found in each region, which allows the user to determine
the available techniques are likely to work. In this paper, we show three case
studies, including SpecInt's gzip, and Mat2C's capacitor, and Nasa7's Vpenta,
and follow up with results which compare actual parallelization results of a
benchmark suite against the results predicted by p-ray.&lt;p&gt;Pre-2018 CSE...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/5gk6v3fx</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Garcia, Saturnino</name>
      </author>
      <author>
        <name>Louie, Christopher</name>
      </author>
      <author>
        <name>Jeon, Donghwan</name>
      </author>
      <author>
        <name>Kota Venkata, Sravanthi</name>
      </author>
      <author>
        <name>Gupta, Anshuman</name>
      </author>
      <author>
        <name>Taylor, Michael</name>
      </author>
    </item>
    <item>
      <title>Experience in Building a Comparative Performance Analysis Engine for a Commercial System</title>
      <link>https://escholarship.org/uc/item/5gh377sq</link>
      <description>Performance testing is a standard practice for evolving systems to detect performance issues proactively. It samples various performance metrics that will be compared with a stable baseline to judge whether the measurement data is abnormal. This type of comparative analysis requires domain expertise, which can take experienced performance analysts days to conduct. In an effort to build an automatic solution for a leading data warehousing company to improve the comparative performance analysis efficiency, we implemented machine learning approaches proposed by existing research. But the initial result has a 86% false negative rate on average, which means the majority of performance defects would be missed. To investigate causes for this unsatisfying result, we take a step back to revisit the performance data itself and find several important data related issues that are overlooked by existing work. In this paper, we discuss in detail these issues and share our hindsights to address...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/5gh377sq</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Huang, Peng</name>
      </author>
      <author>
        <name>Schechter, Craig</name>
      </author>
      <author>
        <name>Chen, Vincent</name>
      </author>
      <author>
        <name>Hill, Steven</name>
      </author>
      <author>
        <name>Shen, Dongcai</name>
      </author>
      <author>
        <name>Zhou, Yuanyuan</name>
      </author>
      <author>
        <name>Saul, Lawrence</name>
      </author>
    </item>
    <item>
      <title>S2Sim: Smart Grid Swarm Simulator</title>
      <link>https://escholarship.org/uc/item/5b87j38b</link>
      <description>The Smart Grid is drawing attention from various research areas. Distributed control algorithms at different scales within the grid are being developed and deployed; yet their effects on each other and the grid's health and stability has not been sufficiently studied due to the lack of a capable simulator. Simulators in the literature can solve the power flow by modeling the physical system, but fail to address the cyber physical aspect of the smart grid with multiple agents. To answer these questions, we have developed S2Sim: Smart Grid Swarm Simulator. S2Sim allows any object within the grid to have its own independent control, transforming physical elements into cyber-physical representations. Objects can have any size ranging from a light bulb to a whole microgrid and their representative data can be supplied from a real device, simulation, distributed control algorithm or a database. S2Sim shields the complexity of the power flow solution from the control algorithms and directly...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/5b87j38b</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Akyurek, Alper Sinan</name>
      </author>
      <author>
        <name>Akslani, Baris</name>
      </author>
      <author>
        <name>Rosing, Tajana Simunic</name>
      </author>
    </item>
    <item>
      <title>Experience Report: an AP CS Principles University Pilot</title>
      <link>https://escholarship.org/uc/item/5754j51b</link>
      <description>We report on the development and deployment of a pilot of the new
Advanced Placement CS Principles course in the United States.  The course is
designed to introduce core computational concepts and instill computational
thinking practices.  We report on an initial offering with 571 university
students, mostly non-CS majors taking the course as a general education
requirement.  We discuss the instructional design supporting the course,
describe how the various components were implemented, and review student work
and valuation of the course.  Though the course appears to “teach
programming” in Alice, students reported gaining significant analysis and
communication skills they could use in their daily life.  We reflect on how
instructional design decisions are likely to have supported this experience and
consider the implications for other K-12 computing/IT education efforts as well
as for regular CS1 courses.&lt;p&gt;Pre-2018 CSE ID: CS2011-0965&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/5754j51b</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Simon, Beth</name>
      </author>
      <author>
        <name>Esper, Sarah</name>
      </author>
      <author>
        <name>Quintin, Cutts</name>
      </author>
    </item>
    <item>
      <title>Quill: Exploiting Fast Non-Volatile Memory by Transparently Bypassing the File System</title>
      <link>https://escholarship.org/uc/item/54g6w2g5</link>
      <description>Fast non-volatile memories will soon make their appearance on the
processor memory bus.  They offer the potential for extremely low-latency,
high-bandwidth access to persistent files.  However, existing interfaces will
impose large system call and file system overheads on those accesses,
squandering the memories' performance.  At the same time, we would like to
leverage existing file systems as much as possible, to reduce the cost of
adopting these new storage technologies. We present a user space library,
called Quill, that avoids system call overheads on most accesses by interposing
on file operations and converting them into memory operations.  Quill enforces
the protections that the file system provides by transferring protection
information into the process's page table and accessing files directly via load
and store instructions.  We describe the Quill system and compare it to a
conventional software stack accessing the same storage device.&lt;p&gt;Pre-2018 CSE ID: CS2013-0991&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/54g6w2g5</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Eisner, Louis Alex</name>
      </author>
      <author>
        <name>Mollov, Todor</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>Personal Pollution Monitoring: Mobile Real-Time Air-Quality in Daily Life</title>
      <link>https://escholarship.org/uc/item/52m1h315</link>
      <description>Poor air quality is a growing global health concern that impacts
millions of people worldwide. Although we are beginning to understand the
health impacts of air pollution, it remains a challenge to provide people with
the information they need to be able to make health-conscious choices. The
CitiSense system gives individuals the real-time tools they need to be able to
identify when and where they are exposed to poor air. We present the results of
a qualitative study regarding a 4-week “in the wild” deployment of the
CitiSense air-quality sensor and system. We focus on how the 16 participants
responded to their new-found information about their environment, how they
shared information, and what kinds of actions were enabled by having access to
real-time air-quality data. Quantitative data gathered through the course of
the study frames participant responses by showing what levels of pollution were
experienced and what activities heightened exposure. We found that
CitiSense’s real-time...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/52m1h315</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Bales, Elizabeth</name>
      </author>
      <author>
        <name>Nikzad, Nima</name>
      </author>
      <author>
        <name>Ziftci, Celal</name>
      </author>
      <author>
        <name>Quick, Nichole</name>
      </author>
      <author>
        <name>Griswold, William</name>
      </author>
      <author>
        <name>Patrick, Kevin</name>
      </author>
    </item>
    <item>
      <title>Improving the Speed and Scalability of Distributed Simulations of Sensor Networks</title>
      <link>https://escholarship.org/uc/item/51v4s0p7</link>
      <description>Distributed simulation techniques are commonly used to improve the
speed and scalability of simulators for wireless sensor networks. However,
accurate simulations of dynamic interactions of sensor network applications
incur large synchronization overheads and severely limit the performance of
existing distributed simulators. In this paper, we present two novel techniques
that significantly reduce such overheads by minimizing the number of sensor
node synchronizations during simulations. These techniques work by exploiting
radio and MAC specific characteristics without reducing simulation accuracy. In
addition, we present a new mechanism that makes it possible to exploit any
potential application specific characteristics for synchronization reductions.
We implement and evaluate these techniques in a cycle accurate distributed
simulation framework that we developed based on Avrora, a popular parallel
sensor network simulator. In our experiments, the techniques achieve a speedup
from...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/51v4s0p7</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Jin, Zhong-Yi</name>
      </author>
      <author>
        <name>Gupta, Rajesh</name>
      </author>
    </item>
    <item>
      <title>Restructuring DNS Log Data for Faster Querying and Optimizing Resource Usage on a Hadoop Cluster</title>
      <link>https://escholarship.org/uc/item/51t2h7xv</link>
      <description>Log data from DNS resolvers contain rich information that is quite
useful for various research use cases such as estimating the popularity of
websites. Log data from approximately 39k resolvers has been collected and
stored on HDFS. The data is so huge and not optimally structured that it takes
a lot of time and resources to search records of interest from the the log. In
this project, we investigate techniques to port the log data to a new format so
that it speeds up the query time and takes less resources both to store the
data and to query the data. We investigated bzip compression,
reformatting/pruning unessential records and partitioning the records into
separate buckets and from our experiments, we found that using a combination of
reformatting/pruning records with partitioning and efficiently sorting the
records based on multiple fields speeds up the domain query by 6 times and
takes approximately 8 times less resources to query in comparison with
unstructured data. Also,...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/51t2h7xv</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Dhakshinamurthy, Prabu</name>
      </author>
    </item>
    <item>
      <title>NVTM: A Transactional Interface for Next-Generation Non-Volatile Memories</title>
      <link>https://escholarship.org/uc/item/4wm358ht</link>
      <description>Advanced non-volatile, solid-state storage technologies such as
phase change memory promise enormous gains in performance relative to both
conventional disks and flash memory-based storage devices.  However, existing
abstractions for accessing non-volatile data (i.e., file systems and the
associated system calls) cannot exploit the performance and flexibility these
memories offer.  We describe a new, transaction-based interface that allows
programmers to implement fast, scalable, durable data structures that are
robust in the face of unexpected system failures.  The interface maps the
non-volatile storage directly into the application's address space and allows
volatile and non-volatile data structures to interact seamlessly in programs.
Since the interface removes the operating system from the critical path of
basic read and write operations, it can realize up to 2350X speedups relative
to transactional storage systems that target the conventional file-based
interface.  We describe...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4wm358ht</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Coburn, Joel</name>
      </author>
      <author>
        <name>Caulfield, Adrian</name>
      </author>
      <author>
        <name>Grupp, Laura</name>
      </author>
      <author>
        <name>Adel, Ameen</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>From ARIES to MARS: Reengineering Transaction Management for Next-Generation, Solid-State Drives</title>
      <link>https://escholarship.org/uc/item/4w79f9rb</link>
      <description>Systems that provide powerful transaction mechanisms often rely on
write-ahead logging (WAL) implementations that were designed with slow,
disk-based systems in mind.  The emerging class of fast, byte-addressable,
non-volatile memory (NVM) technologies (e.g., phase change memories,
spin-torque MRAMs, and the memristor), however, present performance
characteristics very different from both disks and flash-based SSDs.  This
paper addresses the problem of designing a WAL scheme optimized for these fast
NVM-based storage systems.  We examine the features that a system like ARIES, a
WAL algorithm popular for databases, must provide and separate them from the
implementation decisions ARIES makes to optimize for disk-based systems.  We
design a new NVM-optimized WAL scheme (called MARS) in tandem with a novel SSD
multi-part atomic write primitive that combine to provide the same features as
ARIES does without any of the disk-centric limitations.  The new atomic write
primitive makes...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4w79f9rb</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Coburn, Joel</name>
      </author>
      <author>
        <name>Bunker, Trevor</name>
      </author>
      <author>
        <name>Gupta, Rajesh K</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>An Optimization Methodology for Matrix Computation Architectures</title>
      <link>https://escholarship.org/uc/item/4w71405x</link>
      <description>Matrix computations such as matrix decomposition and inversion are
essential for various algorithms which are employed in wireless communication.
FPGAs are ideal platforms for such applications; however, the need for vast
amounts of customization throughout the design process of a matrix computation
core can overwhelm the designer. This paper presents an automatic generation
and optimization methodology for different matrix computation architectures
using a generator tool, GUSTO, that we developed to enable easy design space
exploration with different parameterization options. We especially concentrate
on wireless communication MIMO-OFDM applications which often use small matrix
dimensions. We present automatic generation of a variety of general purpose
matrix computation architectures and optimized application specific
architectures. GUSTO’s application specific architectures have comparable
results to published architectural implementations, but offer the advantage of
providing...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4w71405x</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Irturk, Ali</name>
      </author>
      <author>
        <name>Benson, Bridgit</name>
      </author>
      <author>
        <name>Laptev, Nikolay</name>
      </author>
      <author>
        <name>Kastner, Ryan</name>
      </author>
    </item>
    <item>
      <title>NetBump: User-extensible Active Queue Management with Bumps on the Wire</title>
      <link>https://escholarship.org/uc/item/4w0246js</link>
      <description>Engineering large-scale data center applications built from
thousands of commodity nodes requires both an underlying network that supports
a wide variety of traffic demands, and low latency at microsecond timescales.
Many ideas for adding innovative functionality to networks, especially active
queue management strategies, require either modifying packets or performing
alternative queuing to packets in-flight on the data plane.  However,
configuring packet queuing, marking, and dropping is challenging, since
buffering in commercial switches and routers is not programmable. In this work,
we present NetBump, a platform for experimenting with, evaluating, and
deploying a wide variety of active queue management strategies to network data
planes with minimal intrusiveness and at low latency.  NetBump leaves existing
switches and endhosts unmodified by acting as a ``bump on the wire,''
examining, marking, and forwarding packets at line rate in tens of microseconds
to implement a variety...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4w0246js</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Porter, George</name>
      </author>
      <author>
        <name>Kapoor, Rishi</name>
      </author>
      <author>
        <name>Das, Ambit</name>
      </author>
      <author>
        <name>Al-Fares, Mohammad</name>
      </author>
      <author>
        <name>Weatherspoon, Hakim</name>
      </author>
      <author>
        <name>Prabhakar, Balaji</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
    </item>
    <item>
      <title>Composable Chat: Towards a SOA-based Enterprise Chat System</title>
      <link>https://escholarship.org/uc/item/4qj0p4w7</link>
      <description>Enterprise Chat has emerged as one of the key tools for rapid
communication, decision making, and situational awareness across a wide
spectrum of application domains, ranging from massively multi-player online
games (MMOs) to multi-national corporations to public safety and defense. This
report is motivated by the increasing need to flexibly bridge multiple existing
and emerging standards and technology platforms for Enterprise Chat. A
promising approach to this effect is the use of Service-Oriented Architecture
methodology and technology, as this combination has been used successfully
across the industry in other enterprise integration projects. To determine the
viability of this approach, we have performed a case study on the use of an
SOA-based approach to unifying disparate IM/chat systems into a
system-of-systems framework. This approach leverages enterprise-wide services,
but without risking the IM/chat systems’ existing functionality.  In
collaboration with the Space and...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4qj0p4w7</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Demchak, Barry</name>
      </author>
      <author>
        <name>Krueger, Ingolf</name>
      </author>
    </item>
    <item>
      <title>Pinpoint: Identifying Packet Loss Culprits Using Adaptive Sampling</title>
      <link>https://escholarship.org/uc/item/4p74g215</link>
      <description>Accurately estimating all link-level properties of a large network
has proven to be very difficult.  The measurements used for these estimates
require significant collaboration from all endpoints on the network,
significantly reducing their applicability for large scale Internet
measurements. We present a scalable approach using a small number of hosts
without collaboration from existing routers and minimal collaboration between
the hosts. Our approach is based on adaptive sampling. Initially, each host
probes a set of receivers at a low frequency.  When packet losses are detected,
the sampling rate increases. By detecting correlations between time series and
combining them with information about network connectivity, the host identifies
a set of suspected lossy routers. Hosts then communicate with each other,
combining evidence to identify routers with high packet loss. Our experiments
show that using a relatively small set of hosts and receivers, we can gather
sufficient evidence...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4p74g215</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Ettinger, Evan</name>
      </author>
      <author>
        <name>McFee, Brian</name>
      </author>
      <author>
        <name>Freund, Yoav</name>
      </author>
    </item>
    <item>
      <title>Sampled Simulation for Multithreaded Processors</title>
      <link>https://escholarship.org/uc/item/4nr7f343</link>
      <description>Microarchitectural simulation of multithreaded architectures with
shared resources, such as simultaneous multithreading (SMT) cores and
multi-core processors with shared caches, is time-consuming and the results of
simulation may be dicult to interpret. It is time-consuming because modern
benchmarks run for hundreds of billions (or even trillions) of instructions,
and accurate multi-core and SMT simulation requires higher-detail models than
single-threaded simulation.  The statistics collected when two programs execute
together can be dicult to interpret because the programs both exhibit
independent phase behavior and affect each other's execution.  Starting one
program slightly later than during the original execution will change the
phases that execute together and thus change the eects that the programs have
on each other. &lt;p&gt; Accurate sampled simulation requires accurate sample
collection. We evaluate techniques to improve sampling accuracy and
performance, both for single-threaded...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4nr7f343</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>VanBiesbrouck, Michael</name>
      </author>
    </item>
    <item>
      <title>Analysis and Extension of Arc-Cosine Kernels for Large Margin Classification</title>
      <link>https://escholarship.org/uc/item/4hr514qs</link>
      <description>We investigate a recently proposed family of positive-definite
kernels that mimic the computation in large neural networks.  We examine the
properties of these kernels using tools from differential geometry;
specifically, we analyze the geometry of surfaces in Hilbert space that are
induced by these kernels.  When this geometry is described by a Riemannian
manifold, we derive results for the metric, curvature, and volume element.
Interestingly, though, we find that the simplest kernel in this family does not
admit such an interpretation.  We explore two variations of these kernels that
mimic computation in neural networks with different activation functions.  We
experiment with these new kernels on several data sets and highlight their
general trends in performance for classification.&lt;p&gt;Pre-2018 CSE ID: CS2011-0972&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4hr514qs</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Cho, Youngmin</name>
      </author>
      <author>
        <name>Saul, Lawrence</name>
      </author>
    </item>
    <item>
      <title>Wide-Area Group Membership for Tightly-Coupled Services</title>
      <link>https://escholarship.org/uc/item/4gp4r437</link>
      <description>Today’s large-scale services generally exploit loosely-coupled
architectures that restrict functionality requiring tight cooperation (e.g.,
leader election, synchronization, and reconfiguration) to a small subset of
nodes. In contrast, this work presents a way to scalably deploy tightly-coupled
distributed systems that require significant coordination among a large number
of nodes in the wide area. Our design relies upon a new reliable group
membership abstraction to ensure that either group members are capable of
communicating or that new groups form. In particular, we deploy a distributed
rate limiting (DRL) service within a global testbed infrastructure. Unlike most
distributed services, DRL can safely operate in separate partitions
simultaneously, but requires timely snapshots of global state within each. Our
DRL implementation leverages our proposed group membership abstraction and a
robust gossip-based communication protocol, conjoining the fates of view
maintenance and...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4gp4r437</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Webb, Kevin C</name>
      </author>
      <author>
        <name>Vattikonda, Bhanu C</name>
      </author>
      <author>
        <name>Yocum, Kenneth</name>
      </author>
      <author>
        <name>Snoeren, Alex C</name>
      </author>
    </item>
    <item>
      <title>Mencius: Building Efficient Replicated State Machines for WANs</title>
      <link>https://escholarship.org/uc/item/4f90w1zq</link>
      <description>We present a protocol for general state machine replication -- a
method that provides strong consistency -- that has high performance in a
wide-area network. In particular, our protocol Mencius has high throughput
under high client load and low latency under low client load even under
changing wide-area network environment and client load. We develop our protocol
as a derivation from the well-known protocol Paxos. Such a development can be
changed or further refined to take advantage of specific network or application
requirements.&lt;p&gt;Pre-2018 CSE ID: CS2008-0930&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4f90w1zq</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Mao, Yanhua</name>
      </author>
      <author>
        <name>Junqueira, Flavio</name>
      </author>
      <author>
        <name>Marzullo, Keith</name>
      </author>
    </item>
    <item>
      <title>ASIC Clouds: Specializing the Datacenter</title>
      <link>https://escholarship.org/uc/item/4bf9f938</link>
      <description>GPU and FPGA-based clouds have already demonstrated the promise of accelerating computing-intensive workloads with greatly improved power and performance. In this paper, we examine the design of ASIC Clouds, which are purpose-built datacenters comprised of large arrays of ASIC accelerators, whose purpose is to optimize the total cost of ownership (TCO) of large, high-volume chronic computations, which are becoming increasingly common as more and more services are built around the Cloud model. On the surface, the creation of ASIC clouds may seem highly improbable due to high NREs and the inflexibility of ASICs. Surprisingly, however, large-scale ASIC Clouds have already been deployed by a large number of commercial entities, to implement the distributed Bitcoin cryptocurrency system. We begin with a case study of Bitcoin mining ASIC Clouds, which are perhaps the largest ASIC Clouds to date. From there, we design three more ASIC Clouds, including a YouTube-style video transcoding...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4bf9f938</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Magaki, Ikuo</name>
      </author>
      <author>
        <name>Khazraee, Moein</name>
      </author>
      <author>
        <name>Gutierrez, Luis Vega</name>
      </author>
      <author>
        <name>Taylor, Michael Bedford</name>
      </author>
    </item>
    <item>
      <title>BuildingSherlock: Fault Management Framework for HVAC Systems in Commercial Buildings</title>
      <link>https://escholarship.org/uc/item/49d79511</link>
      <description>HVAC systems constitute 40% of energy in commercial buildings, and faults in HVAC account for 5% to 20% of its energy consumption. Typically, HVAC in modern buildings are managed using Building Managing Systems (BMS), and fault detection is one of the essential services provided by BMS to keep HVAC operational. We study the fault management practices followed in real commercial buildings, and find that current techniques used for fault detection fail to detect large number of efficiency related faults. Based on our findings, we developed BuildingSherlock (BDSherlock), which is a web service based fault management framework that exposes building information to automatically detect faults using useful algorithms. We deploy BDSherlock in a 145000 sqft building at UC San Diego, successfully detected 87 faults using data driven analysis.&lt;p&gt;Pre-2018 CSE ID: CS2014-1007&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/49d79511</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Teraoka, Hidetoshi</name>
      </author>
      <author>
        <name>Balaji, Bharathan</name>
      </author>
      <author>
        <name>Zhang, Rizhen</name>
      </author>
      <author>
        <name>Nwokafor, Anthony</name>
      </author>
      <author>
        <name>Narayanaswamy, Balakrishnan</name>
      </author>
      <author>
        <name>Agarwal, Yuvraj</name>
      </author>
    </item>
    <item>
      <title>The Harey Tortoise: Managing Heterogeneous Write Performance in SSDs</title>
      <link>https://escholarship.org/uc/item/49297740</link>
      <description>Recent years have witnessed significant gains in the adoption of
flash technology due to increases in chip bit density, enabling higher
capacities and lower prices. Unfortunately, these improvements come at a
significant cost to performance with trends pointing toward worst-case flash
program latencies on par with disk writes. We extend a conventional flash
translation layer to schedule flash program operations to flash pages based on
the operations' performance needs and the pages' performance characteristics.
We then develop policies to improve in two scenarios: First, we improve peak
performance for latency-critical operations of short bursts of intensive
activity by 36%.  Second, we realize steady-state bandwidth improvements of up
to 95% by rate-matching garbage collection performance and external access
performance.&lt;p&gt;Pre-2018 CSE ID: CS2013-0996&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/49297740</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Grupp, Laura</name>
      </author>
      <author>
        <name>Davis, John D</name>
      </author>
      <author>
        <name>Swanson, Steven</name>
      </author>
    </item>
    <item>
      <title>Signal Probability based Statistical Timing Analysis</title>
      <link>https://escholarship.org/uc/item/47h846gc</link>
      <description>We observe that Monte Carlo (SPICE) simulation provides the most
accurate and trustable statistical timing analysis, while the existing SSTA
method has completely ignored the effect of input statistics on chip timing
performance, and provides either accurate estimate nor pessimistic bound of the
actual chip timing performance statistics. We propose signal probability (i.e.,
the logic one occurrence probability for a signal) based statistical timing
analysis for improved accuracy and reduced pessimism over the existing SSTA
methods, and improved efficiency over Monte Carlo (SPICE) simulation. Our
experimental results show that our proposed SPSTA computes mean (standard
deviation) of signal arrival times within 6.2% (18.6%), while SSTA computes
mean (standard deviation) of signal arrival times within 13.40% (64.3%) of
Monte Carlo simulation results; SPSTA also provides signal probaiblity
estimation within 14.28% of Monte Carlo simulation results for the ISCAS'89
benchmark circuits.
&lt;p&gt;Pre-2018...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/47h846gc</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Liu, Bao</name>
      </author>
    </item>
    <item>
      <title>A Randomized Algorithm for Label Assignment in Dynamic Networks</title>
      <link>https://escholarship.org/uc/item/46d93544</link>
      <description>A basic problem in distributed computing has to do with assigning
unique labels --- that is, names or addresses --- to network elements. Some
approaches to solving this problem include using static assignment (e.g., MAC
addresses), or using a centralized authority (e.g., DHCP). In this paper, we
present an approach that is suitable for dynamic environments: where the rules
constraining the label choices depend on the network topology, which in turn
can change. This problem arose in the context of automatic address assignment
in large-scale data center networks, and so we consider issues such as the
scalability of message load and convergence time. We give a new algorithm,
called the Decider/Chooser Protocol, and show its use in the assignment of
labels in data center networks.  We evaluate the correctness of the
Decider/Chooser Protocol through proofs and model checking, and explore its
performance via mathematical analysis and simulation.  Through this evaluation,
we find that...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/46d93544</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Walraed-Sullivan, Meg</name>
      </author>
      <author>
        <name>Niranjan Mysore, Radhika</name>
      </author>
      <author>
        <name>Marzullo, Keith</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
    </item>
    <item>
      <title>Prostate Cancer Detector for Pathology Images</title>
      <link>https://escholarship.org/uc/item/4272w41n</link>
      <description>Availability of slide scanners and electronic medical record systems
have led to increased digitization of pathology images. With digitization,
Computer-Aided Diagnosis (CAD) tools can be built to reduce pathologist's
fatigue and improve diagnosis workflow. As a first step towards building such
tools, we developed a cancer detector for prostate needle core biopsy images.
The detector is trained using boosting. We use color and texture features. We
also built new structural features that express visual cues not captured by
color and texture features. These structural features inform the classifier
whether cancer has deformed the glands, the main functional unit of prostate.
On the test images we scored, we got an Area Under the ROC Curve (AUC) of 0.94.&lt;p&gt;Pre-2018 CSE ID: CS2012-0987&lt;/p&gt;</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4272w41n</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>Kabra, Mayank</name>
      </author>
      <author>
        <name>Baird, Stephen</name>
      </author>
      <author>
        <name>Mahooti, Sepi</name>
      </author>
      <author>
        <name>Kim, Jihoon</name>
      </author>
      <author>
        <name>Ohno-Machado, Lucila</name>
      </author>
      <author>
        <name>Freund, Yoav</name>
      </author>
    </item>
    <item>
      <title>Practical Market-Based Resource Allocation</title>
      <link>https://escholarship.org/uc/item/4210s00j</link>
      <description>Resource allocation continues to be one of the primary challenges in
federated computing systems.  Currently, users are forced to either suffer the
delays inherent to batch scheduling used by the supercomputing community or the
tragedy of the commons that befalls propotional share allocation as employed on
PlanetLab.  Market-based schemes have repeatedly been proposed as a possible
solution but none have yet to see wide deployment. We present our initial
experience with two operational auction-based schedulers---one for PlanetLab,
the other for a large SensorNet testbed---and propose two key mechanisms to
combat the challenges faced by real-world use of economic schedulers.  Our
experience shows that some users are unwilling or unable to accept the
uncertainty of an auction; hence, we develop a buy-it-now mechanism that allows
risk-averse users to instantly acquire resources at a price premium. Further,
we describe how intelligent monetary policy, in particular the judicious use...</description>
      <guid isPermaLink="true">https://escholarship.org/uc/item/4210s00j</guid>
      <pubDate>Tue, 14 Mar 2023 00:00:00 +0000</pubDate>
      <author>
        <name>AuYoung, Alvin</name>
      </author>
      <author>
        <name>Chun, Brent</name>
      </author>
      <author>
        <name>Ng, Chaki</name>
      </author>
      <author>
        <name>Parkes, David</name>
      </author>
      <author>
        <name>Vahdat, Amin</name>
      </author>
      <author>
        <name>Snoeren, Alex C</name>
      </author>
    </item>
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