CMP faces numerous challenges, as we move towards 45-nm and 32-nm nodes. The most important of these, as identified by ITRS , are: a) reliably predicting and controlling post-CMP topography (dishing and erosion loss should be limited to within 10% of the interconnect height throughout the die); b) Integration of ultra low-K
dielectric materials, including predicting stresses and damage, and designing very low stress polishing processes; and c) designing new planarization processes for new materials and new requirements.
To address these, a multi-scale (feature/die/wafer) CMP modeling framework is being developed for enabling Design for Manufacturing (DfM) and Manufacturing for Design (MfD). Topographic evolution has been studied for Shallow Trench Isolation CMP and is now being extended to copper CMP. A detailed, quantitative understanding of the mechanism(s) of CMP is being elucidated, using fundamental experiments and a mechanistic model based on physical data. Stress issues in low-K dielectric during copper CMP, which can lead to fracture and delamination, are being studied using Finite Element Modeling.