In the past decades, semiconductor industry has been enhancing the performance of silicon-based processor through downsizing the size of transistors. However, miniaturization is approaching the physical limits. Difficulties like floating gate interference, low coupling ratio, and heat dissipation are increasingly severe. Therefore, nanoscale magnetic logic system, as a prominent alternative technology, is being studied.
A theoretical study is reported to use a patterned network of nanomagnets (nanocells) as a new architecture for next-generation computing processors, in which the direction of the magnetization represents a binary signal in each cell.
Such shape-insensitive nanomagnetic devices can relieve severe fabrication constraints associated with building nanomagnetic cells of narrowly defined shapes. Particularly, comparison between materials with in-plane and out-of-plane crystalline anisotropy is presented. Properties of materials with in-plane crystalline anisotropy can be tailored to match those of shape-induced longitudinal nanomagnets while materials with out-of-plane anisotropy could enable a new set of features. For instance, besides the key features of any magnetic logic, i.e., non-volatility, low-power consumption, and radiation hardness, some of the new features of the out-of-plane materials include (i) cost-effective fabrication, (ii) scalability to sub-10-nm dimensions, and (iii) their natural ability to be extended into a three-dimensional (3-D) physical space which opens a new era of technology opportunities.
Implementation of a high density three-layer magnetic recording device is introduced. It proves the feasibility of using multilayer nanomagnetic material with perpendicular anisotropy to store 2N levels of signal (N is the amount of magnetic layers). Related experimental results are demonstrated. Moreover, similar three-dimensional four-layer architecture is proven to be a potential candidate of building majority logic gates.
Development of energy-efficient spin-transfer torque (STT) magnetization reversal in sub-10nm magnetic tunneling junction (MTJ) point contacts is also explored. Reducing required switching current of STT-MTJ is an essential and practical issue in the manufacturing industry of STT-based MRAM. Both simulation and experimental results show the switching current requirement is at least an order magnitude less in devices of length in sub-10nm region, which has great importance for developing next generation MRAM. Besides, experimental results show there is little relevance between contact resistance and the TMR effect amplitude.