Accompanying and enabling the explosion of information technology in the recent decades, RF CMOS design has grown into a mature discipline and a multi-billion industry, and CMOS radio transceivers can be found in almost every consumer electronic devices nowadays. To enable the next generation RF CMOS applications, advances in both system and circuit techniques need to be accomplished. This work presents several of these advances, specifically in the context of the data communication application and low noise circuit techniques.
First, a new wideband receiver architecture suitable for wireless communication is proposed and analyzed. The architecture has both phase and thermal noise cancellations to significantly relax the trade-offs between VCO phase noise and LOGEN power consumption, and trade-offs between noise, out-of-band linearity, and wide input bandwidth.
Next, a current-mode mm-wave receiver architecture is described. The mm-wave receiver relies on current mode operation and novel techniques in passive devices to achieve wide RF bandwidth, low noise, and high out-of-channel linearity. It considers mm-wave receivers' adjacent/alternative channel blocking scenarios for the first time.
Finally, a high speed on-chip RF-Interconnect with quarter-wavelength directional coupler for bi-direction communication and multi-drop arbitration is presented. The proposed system introduces an emerging on-chip interconnect solution with superior latency and power efficiency. It also brings tremendous flexibility and re-configurability, which proves to be extremely beneficial to the next generation large scale Network-on-Chip (NoC) system.