We define the nonlinear dynamic phenomenon of AM to PM distortion and discuss different candidate mechanisms. Qualitative descriptions of this from of distortion are turned into expressions, and are applied to FET RF power amplifier described in the literature. Most importantly, we are able to identify the dominant mechanism of AM-PM distortion in various practical circuits, which then suggests methods of remediation. Our theory is shown to match simulations and measurements.

We study the jitter performance of multiplying delay locked loops (MDLLs) and provide an effective approach to derive the phase noise of open loop MDLLs. We demonstrate that the ring oscillator phase noise models from Abidi and Hajimiri are essentially the same. Based on the analysis for MDLL jitter performance, new system models for Edge Combining DLLs and Recirculating DLLs are proposed which are accurate and simple for stability and noise analysis. Moreover, spurs caused by mismatch errors in Edge Combining DLLs are studied based on the new system model.

Mixed signal circuit design often involves circuits that are time-varying or highly non-linear, which further results in systems that are difficult to characterize using established methodologies for linear time-invariant systems, thus designers are more than often forced to rely on intensive simulations for design. This dissertation explores design optimization for comparators, phase locked loops and ADC from three different perspectives.

First, a complete analysis for regenerative comparators is presented including noise, offsets and speed for the first time. Despite the fact that the comparators are time-varying and regenerative with infinite gain, simple equivalent circuits still accurately capture their operation. Design guideline are provided for different comparator architectures.

Second, a linearized analysis for phase locked loops using bang-bang phase detectors is presented. The high non-linear bang-bang phase detector is ascribed to an effective gain, whose physical meaning is interpreted in signal space. Closed form expressions for loop gain, output jitter and phase noise profile are obtained using transfer functions for the first time. Design guidelines are also provided.

Last, a 2.5GS/s 10bit 65mW ADC in 28nm CMOS FD-SOI without active amplifier and intensive digital calibration is presented. This highlights the potential of circuit design based on complete understandings. The fabricated ADC with considerably less complexity achieves comparable performance with state-of-arts. Different imperfections are quantitatively studied and compared with measurement.

In the past decade, there has been a great interest in bionic and neural implantable electronics to investigate the human body's working, to understand different physiological conditions, and to cure disease. Among them, neuromodulation systems have been found by the neuroscience community as a promising tool to decode the functioning of the brain, and an alternative strategy for diagnosis and treatment of neuropsychiatric disorders. Today's clinical neuromodulation systems, however, may suffer from many serious constraints. For instance, many are wired refrigerator-size electronic setups, which immobilize the patient, increase the risk of infections, and have a limited duration of operation. The next generation of neuromodulation systems should contain a robust, energy-efficient solution to deliver wireless data and power.

In this work, first, we present an implantable distance-immune ultra low-power data link which would be used in a biomedical implant that most of the time relays monitoring data to a unit outside the human body. The near-field data link is based on a free-running oscillator tuned by coupled resonators. We have studied the properties of the inductively-coupled link and derive its key features and constraints. After understanding the design space, we have designed and built transceiver chips in 40 nm CMOS technology which enable a bidirectional wireless connectivity. Data can be transferred in half-duplex at up to 4 Mbps in a Load Shift Keyed (LSK) uplink, and up to 2 Mbps in an ASK downlink. With one automatic adjustment, the link can maintain a reasonable error rate of less than 10−6 (BER< 10−6) over coil separations of up to 4.5 cm.

In monitoring body/brain activities, with an air data rate of 4 Mbps, this wireless link can multiplex 16b-words acquired at 0.5 kS/s from each of up to 500 neural probes. Typically, the implant will transmit data on the uplink most of the time; the circuit reported here is optimized for this function, consuming less than 0.1 pJ/bit at 4 Mbps. When receiving on the downlink at 2 Mbps, the implant consumes 5 pJ/bit.

Second, we have integrated the designed data link in a state-of-the-art, human-quality implantable neuromodulation system, and verified its communication performance in benchtop and in-vitro environments. The data link achieved a maximum range of 3 cm packaged in a titanium can and using a bio-compatible coil.

Third, we describe a Medium Access Control (MAC) system for the designed transceivers (PHY layer). The MAC layer is designed as a stand-alone accelerator on an FPGA platform, capable of handling incoming and outgoing data in parallel. In the next generation of the

data link, we can migrate this to an Application Specific Integrated Circuit (ASIC) to reduce the power consumption and the system form factor.