One of the main challenges of In-Band Full-Duplex (IBFD) communication systems is the mitigation of Self-Interference (SI). Most popular self-interference suppression techniques involve taking a copy of the transmitted signal and scaling the copy before subtracting it at the receiver to get the desired signal minus the interference. The scaling involves rotating the phase of the copy and modifying its amplitude. However, due to channel variations, the replica of the transmitted signal could be delayed.

Most systems work with the underlying assumption that the baseband signal remains constant over a delay time interval. It is commonly assumed that baseband information signal experiences an insignificant amount of delay. This does not hold true as the modulated bandwidth increases. If this delay effect is taken into consideration when designing the canceller, the canceller’s performance can be improved.

This thesis work analyzes the effects of the baseband signal delay in Single Channel Full Duplex SI Cancellation Systems. The analysis also attempts to investigate the relationship between signal bandwidth on the cancellation capabilities of the system. For this, an RF Cancellation (RFC) block was designed at the Wireless Systems and Circuits Laboratory to be added as a peripheral to the Single Channel RF System. This document details the results of controlled delay experiments conducted on the RF Cancellation Block.

Satellite-based broadband communication has experienced increased growth in Communications on the Move (COTM) platforms such as maritime, commercial aviation, and government aviation. COTM antennas must address the challenge of offering a desired data rate to users using wide beam satellites which are disadvantaged with low gain and asymmetric gain patterns. The new High Throughput Satellite (HTS) designs have large numbers of small spot beams, reuse frequency across the beams, and offer higher EIRP and G/T to address the challenges encountered by COTM. Satellite resources, mainly power and bandwidth, need to be allocated to meet the peak capacity demand in each of the HTS beam rather than the sum of the capacity demand in all HTS beams. This typically results in a larger capacity requirement to satisfy.

The researcher proposes a ground-based solution to plan transmission in HTS beams and dynamically adapt parameters such as bandwidth and transmission power in an HTS equipped with Multi Port Amplifier (MPA) such that the demand for the capacity that changes with time can be met in real time. At any given time, the available power and bandwidth can be assigned to a beam based on its demand by varying the input power levels. Since the conventional transmission in satellite service is fixed and based on the peak demand in each beam, this solution will reduce the satellite resources required to meet the capacity demand and significantly benefit COTM services.

Brain-inspired neuromorphic systems have witnessed rapid development over the last decade from both algorithmic and hardware perspectives. Neuromorphic hardware promises to be more energy- and speed- efficient as compared to traditional Von-Neumann architectures. Thanks to the recent progress in solid-state devices, different nanoscale-nonvolatile memory devices, such as RRAMs (memristors), STT-RAM and PCM, support computations based on mimicking biological synaptic response. The most important advantage of these devices is their ability to be sandwiched between interconnect wires creating crossbar array structures that are inherently able to perform matrix-vector multiplication (MVM) in one step. Despite the great potential of RRAMs, they suffer from numerous nonidealities limiting the performance, including, high variability, asymmetric and nonlinear weight update, endurance, retention and stuck at fault (SAF) defects in addition to the interconnect wire resistance that creates sneak paths. This thesis will focus on the application of RRAMs for neuromorphic computation while accounting for the impact of device nonidealities on neuromorphic hardware.

In this thesis, we first develop a compact SPICE-like framework for the resistive crossbar array that incorporates the RRAM device model and interconnect parasitics such as wire resistance, inductance, capacitance, and conductance. This framework is the corner-stone of the simulation infrastructure developed in this work, allowing for >1000\times faster simulation results as compared to SPICE. Second, we propose novel reading and writing techniques to read and write the entire word in one clock cycle with an optimized bias scheme to minimize the write errors. To complete the memory design, the required reading and writing CMOS peripheral circuits are designed as well. Due to the inevitable existence of the sneak path problem in crossbar arrays, nonstationary polar codes are designed to mitigate the effect of this problem for crossbar-based memory applications showing a significant improvement in bit-error-rate performance.

In the third part, we propose software-level solutions to mitigate the impact of nonidealities, that highly affect the offline (ex-situ) training, without incorporating expensive SPICE or numerical simulations. We propose two techniques to incorporate the effect of sneak path problem during training, in addition to the device's variability, with negligible overhead. The first technique is inspired by the impact of the sneak path problem on the stored weights (devices' conductances) which we referred to as the mask technique. This mask is element-wise multiplied by the weights during the training. This mask can be obtained from measured weights of fabricated hardware. The other solution is a neural network estimator which is trained by our SPICE-like simulator. The test validation results, done through our SPICE-like framework, show significant improvement in performance, close to the baseline BNNs and QNNs, which demonstrates the efficiency of the proposed methods. Both techniques show the high ability to capture the problem for multilayer perceptron networks for MNIST dataset with negligible runtime overhead. In addition, the proposed neural estimator outperforms the mask technique for challenging datasets such as CIFAR10. Furthermore, other nonidealities such as SAF defects and retention are evaluated.

Fourth, we develop a model to incorporate the stochastic asymmetric nonlinear weight update in online (in-situ) training. We propose two solutions for this problem; 1) a compensation technique which is tested on a small scale problem to separate two Laplacian mixed sources using online independent component analysis. 2) stochastic rounding and is tested on a spiking neural network with deep local learning dynamics showing only a 1~2% drop in the baseline accuracy for three different RRAM devices. We also propose Error-triggered learning to overcome the limited endurance problem with only 0.3% and 3% drop in the accuracy for N-MNIST and DVSGesture datasets with around 33x and 100x reduction in the number of writes, respectively.

Finally, the prospects of this neuromorphic hardware are discussed to develop new algorithms with the existing resistive crossbar hardware including its nonidealities.

Recently Full-Duplex (FD) communication has gained significant interest due to demonstrable increase in throughput and spectral efficiency. Conventional Half-duplex (HD) communication systems use either time-duplexing or frequency-duplexing to avoid self-interference. In contrast, full-duplex systems transmit and receive simultaneously on the same frequency band, thus optimally utilizing available resources. The main challenge in FD systems is managing the self-interference (SI) signal at each node, which is typically orders of magnitude larger than the intended signal of interest (SOI). To achieve sufficient SI suppression, FD systems rely on cancellation across multiple domains such as spatial, analog, and digital. However, number of practical, FD specific challenges arise impacting quality of service, when at least one node in a network operates in full-duplex mode.

\par In this thesis, we consider practical issues of wireless networks containing a full-duplex node. The ultimate goal of this work is to design and implement real-time, end-to-end networks consisting of at least one FD node that is capable of improving network performance under limited available bandwidth constraint. First, we identify synchronization issues in a network consisting of a full-duplex base station communicating with half-duplex nodes. Novel synchronization techniques specific for full-duplex networks are proposed that allow compensation of synchronization errors in time and frequency. The proposed techniques are implemented and tested experimentally on a real-time full-duplex wireless network. Second, we characterize the dynamic environment impact on the received self-interference in the FD system, which is equipped with a reconfigurable antenna as a passive SI suppression mechanism. The self-interference channel delay profile is measured using the FD system operating on 5MHz, 10MHz, and 20MHz bandwidths. The measured channel profiles collected under suppressing and non-suppressing antenna patterns are compared, and channel changes in static, as well as dynamic environments, are highlighted. We then statistically model the SI channel by performing probability distribution fitting to SI channel data. Third, the thesis proposes a Wi-Fi compliant self-interference active cancellation technique for amplify and forward, as well as decode and forward full-duplex relays. Finally, we design and implement an end-to-end wireless network extended with the aid of a custom-designed amplify and forward full-duplex relay. We then analyze the relay coverage limitation under the stability and transmit power constraints. The network performance is analyzed as a function of relay location for constant gain and constant transmit power modes, consequently suggesting optimal relay location that will maximize signal to noise plus interference ratio (SINR) at the destination node. We evaluate the overall network performance by simulation, as well as experimentally in outdoor/indoor environments.

With the continued scaling of chip manufacturing technologies, the significance of process variation in performance of the systems is increasing. Specifically, process variation results in growing voltage and frequency overhead margins required to ensure error free operation of circuits. However, the traditional practice of over-designing the systems to cover process variation is no longer an efficient design methodology in an age with high demands for processing power and limited energy supplies. In this dissertation, a novel analytical model is proposed to predict the required margin accurately in the early stages of design space exploration. The model can be used to optimize the system overhead in error free calculations or to release the bound by full correctness in error tolerant parts of systems and optimize the energy vs. performance trade-off. Additionally, this model also considers the statistics of the inputs of the circuit as compared to other existing efforts enabling it to achieve close predictions of full circuit simulation results in a short time. This model is finally used in an adaptive carry select/ripple carry adder configuration to demonstrate the potential achievable power savings.

Growing variation in newer technology nodes is not always a negative side effect. The increased inherent randomness in the process manufacturing technology can be utilized to develop unique physically unclonable functions (PUFs). These functions are irreproducible hardware-based authenticating systems, which do not require memory-based storage. A low overhead delay-based PUF using the variation of the silicon manufacturing is also proposed in the second part of this work. The proposed PUF uses a simple and efficient structure to convert the randomness of the manufacturing process into random responses to fixed challenges in identically designed circuits.