Common, classical computer architectures are based upon few computational cores that collaborate and communicate through larger, slower system memory. In this work, we introduce a configurable, checkerboard grid of processing cells architecture with distributed cores and memories designed to maximize the benefits of parallelization. We explore the checkerboard model and a classical model at a high level to compare their behaviors in a moderately parallelized JPEG encoder application benchmark. The models are simulated with a Loosely-Timed, SystemC TLM-2.0 test platform with timing by processor core, memory, and memory controller, and transaction. Our experimental results show a 66% faster execution speed and higher memory bandwidth headroom for the checkerboard architecture, compared to the classical architecture.

For a system-level design which may be composed of multiple processing elements running

in parallel, various kinds of unwanted consequences may happen if the system

is constructed carelessly. For example, deadlock may happen if improper execution

order and communication between processing elements is used in the system. Another

problem which may be caused by the concurrent execution is race condition, as

shared variables in the system-level model could be accessed by multiple concurrent

threads in parallel. Those unwanted behaviors definitely have negative influence on

the functionality of the system. Furthermore, the functionality is not the only concern

in system design as timing constraints are critical as well. If the system cannot

finish the job within timing constraints, it is still considered an unwanted design. To

address these issues, we propose two formal analysis approaches in this dissertation

to analyze three types of properties we discussed above, which are

1). liveness,

2). satisfiability of timing constraint, and

3). May-Happen-in-Parallel access.

These two approaches are based on Satisfiability Modulo Theories (SMT) and UPPAAL

automaton model respectively. We run these two approaches on our in-house

system models, including a JPEG encoder, MP3 decoder, AMBA AHB and CAN

bus protocol models. The experimental results show our approaches are capable of

analyzing those properties meeting our expectation within reasonable analysis time.

This Language Reference Manual defines the syntax and semantics of the SpecC language. For each SpecC construct the syntax, purpose, and semantics are defined and an explaining example is given. Also the full SpecC grammar is included using a formal notation in lex and yacc style.

In this report we discuss the main models of computation, the basic types of architectures, and language features needed to specify systems. We also give an overview of a generic methodology for designing systems, that include software and hardware parts, from executable specifications.

We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, waitfor, par, pipe, and try statements as they are introduced in SpecC. We present our definition in form of distributed Abstract State Machine (ASM) rules reflecting the specification given in the SpecC Language Reference Manual [5]. We mainly see our formal semantics in three application areas. First, it can be taken as a high-level, pseudo code-oriented specification for the implementation of a SpecC simulator which is outlined in a separate section. Second, it is a concise, unambiguous description for documentation and standardization. Finally, it is a first step for Spece synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets.

In this report, we discuss the characteristics necessary for specifying embedded hardware-software systems. We describe the constructs needed to capture these characteristics and propose a new C based specification language to describe heterogeneous embedded systems.

In this paper, we describe the goals for the development of an executable modeling language in the context of a homogeneous codesign methodology featuring the synthesis, reuse and validation flow. A C based language called SpecC+ is proposed as an attempt to achieve these goals. The syntax and semantics of the language is presented and compared with existing HDLs and we conclude it is conceptually more abstract, syntactically simpler, and semantically richer.