System conceptualization and modeling requires support for both hardware and software components specification, and the ability to do complete system simulation rapidly and accurately. In this paper, we present a system engineering methodology that is built upon the definition and implementation of object relationship. Our approach allows a designer to build an executable, simulatable as well as synthesizable system model using the same language platform. We show how class interfaces can be used for structural representation throughout all design abstraction levels. The object oriented methodology allows IP-Reuse through object libraries and design patterns, and automatic documentation generation. The design process employs an extended and automatic documentation generation. The design process employs an extended UML (Unified Modeling Language) notation and classes from Scenic and ICSP class libraries. We describe our implementation of a prototype that supports our design methodology.

IP component based system-on-chip design demands an integration, architectural trade-off exploration, and verification environment. Such an environment can only be effective, if system integrators can integrate components from libraries easily, with fast turn-around time and can efficiently simulate for functional and performance validation.

The advent of C++ based design libraries such as SystemC, Cynlib, and other similar design environments, such as SpecC, allows IP designers to create C++ component libraries, which are either pre-packaged generic elements, or specialized IP blocks. However, mere availability of such components does not necessarily imply ease of integration, or fast architectural exploration. The designers/system integrators need an environment that allows them to think about composable design elements, as hardware elements, and lets them use such elements without having to go through C++ software engineering cycles, such as intergation coding in C++, recompilation, and the corresponding softvvare problems.

The increasing heterogeneity and complexity of VLSI systems has made the use of C++ popular for building simulation and synthesis models at higher levels of abstraction. Currently, there are several different embodiments of C++ based environments, mostly in the form of hardware modeling libraries built on top of C++. However, the semantic gap between hardware modeling concepts, and the software programming language constructs, poses several issues which require critical examination. In this paper, we address the issue of interoperability between models built using different C++ based modeling libraries, or even modeling "styles" including home-grown C++ models. Model interoperability is the ability to use C++ based descriptions across different C++ based modeling environments. Two important aspects of interoperability are model composability, and model reusability. In this paper we focus on model reusability, analyzing various dimensions of the re usability of C++ based models, in an integration environment for building SOC models. We show how an inheritance based composition may be used to make two distinct C++ based class libraries interoperate. We also outline the implementation of a dynamic composition environment, which allows automatic run-time delegation based composition, to achieve interoperability. These strategies allow system integrators to focus on design composition, rather than software programming details inherent in the current inheritance based solutions.