This paper describes a novel generator-generator language, LEGEND, for the defintion, generation and maintenance of generic component libraries used in high level synthesis. Each LEGEND description generates a library generator GENUS, which is organized as a hierarchy of generic component generators, component templates, and component instances. Component instances from the GENUS library are used by high level synthesis systems to transform the abstract behavior of a design into an interconnection of generic components satisfying this behavior. Although existing hardware description languages such as VHDL are very good for describing component libraries, they lack the capability of generating these component libraries from a higher-level description. LEGEND complements a language such as VHDL by providing a component library generator-generator with behavioral models for simulation and subsequent synthesis. The components in a LEGEND generated library have realistic register transfer semantics, including clocking, asynchrony and data bi-directionality. LEGEND is extensible, since its simple syntax allows users to add new component types or modify existing component types easily. The LEGEND generator-generator is currently implemented on SUN3's under C/UNIX and is used by a suite of behavioral synthesis tools at U.C. Irvine.

This report describes the organization of GENUS, a generic component library for high level synthesis. Generic components and instances in GENUS are organized into hierarchical classes, with the component type stored at the root of the hierarchy, and particular instances stored at the leaves. This permits a consistent representation of generic components which may be used by a variety of synthesis and analysis tools. The appendix contains the description of the GENUS generator library.

Runtime resource management for many-core systems is increasingly complex.

The complexity can be due to diverse workload characteristics with conflicting demands or limited shared resources such as memory bandwidth and power.

Resource management strategies for many-core systems must distribute shared resource(s) appropriately across workloads, while coordinating the high-level system goals at runtime in a scalable and robust manner.

To address the complexity of dynamic resource management in many-core systems, state-of-the-art techniques that use heuristics have been proposed.

These methods lack the formalism in providing robustness against unexpected runtime behavior. One of the common solutions for this problem is to deploy classical control approaches with bounds and formal guarantees.

Traditional control theoretic methods lack the ability to adapt to (1) changing goals at runtime (i.e., self-adaptivity), and (2) changing dynamics of the modeled system (i.e., self-optimization).

In this thesis, I explore adaptive resource management techniques that provide self-optimization and self-adaptivity by employing principles of computational self-awareness, specifically reflection.

By supporting these self-awareness properties, the system will reason about the actions it takes by considering the significance of competing objectives, user requirements, and operating conditions while executing unpredictable workloads.

This paper describes the behavioral modeling of DRACO, a peripheral interface Application Specific Integrated Circuit (ASIC) developed by Rockwell International for numerical control applications. The behavioral model was generated from a data sheet of the fabricated chip, which primarily described the chip's input-output functionality, physical and operational characteristics, and a functional block diagram. The data sheet contained very little abstract behavioral information. This report describes the abstract behavioral model of the DRACO chip, and uses flowcharts and VHDL to capture the behavior. The behavioral model was developed through reverse engineering of the data sheet description, supplemented by further consultation with designers of the DRACO ASIC at Rockwell Intemational. The report describes typical behavioral test sequences that were applied to the DRACO VHDL model to verify its correctness. The appendices contain the original DRACO datasheet and the VHDL code used to capture DRACO's behavior.

The growing computing demands of emerging application domains such as Recognition/Mining/Synthesis (RMS), visual computing, wearable devices and the Internet of Things (IoT) has driven the move towards manycore architectures to better manage tradeoffs among performance, energy efficiency, and reliability.

The memory hierarchy of manycore architectures has a major impact on their overall performance, energy efficiency and reliability. We identify three major problems that make traditional memory hierarchies unattractive for manycore architectures and their data-intensive workloads: (1) they are power hungry and not a good fit for manycores in face of dark silicon, (2) they are not adaptable to the workload's requirements and memory behavior, and (3) they are not scalable due to coherence overheads.

This thesis argues that many of these inefficiencies are the result of software-agnostic hardware-managed memory hierarchies. Application semantics and behavior captured in software can be exploited to more efficiently manage the memory hierarchy. This thesis exploits some of this information and proposes a number of techniques to mitigate the aforementioned inefficiencies in two broad contexts: (1) explicit management of hybrid cache-SPM memory hierarchies, and (2) exploiting approximate computing for energy efficiency.

We first present the required hardware and software support for a software-assisted memory hierarchy that is composed of distributed memories which can be partitioned between caches and software-programmable memories (SPMs) at runtime. This memory hierarchy supports local and remote allocations and data movements between SPM and cache and also between two physical SPMs. The distributed SPM space is shared between a mix of threads where each thread explicitly requests SPM space throughout its execution. The runtime component of this hierarchy shares the entire distributed SPM space between contending threads based on an allocation policy. Unlike traditional memory hierarchies, we incorporate no coherence logic in this hierarchy. The program explicitly allocates the shared data on the distributed SPM space. For all threads of that program, the accesses to shared data are forwarded to the same physical copy.

Next, we augment caches and SPMs in this hierarchy with approximation support in order to improve the energy efficiency of the memory subsystem when running approximate programs. We present approximation techniques for major building blocks of our hybrid cache-SPM memory hierarchy. We introduce Relaxed Cache as an approximate private L1 SRAM cache where the quality, capacity, and energy consumption of this cache are controlled through two architectural knobs (i.e., voltage and the number of acceptable faulty bits per cache block). We then present QuARK Cache, an approximate shared L2 STT-MRAM cache. The read and write current amplitude provide two knobs to make a tradeoff between the accuracy of memory operations and the dynamic energy consumption. We then introduce Write-Skip, a technique that skips write operations in STT-MRAM data SPMs if the previous value and the new value are approximately equal. Finally, we discuss a quality-configurable memory approximation strategy using formal control theory that adjusts the level of approximation at runtime depending on the desired quality for the program's output.

We implemented all software and hardware components of the proposed software-assisted memory hierarchy in the gem5 architectural simulator. Our simulations on a mix of RMS and microbenchmarks show that our proposed techniques achieve better performance, energy, and scalability for manycore systems over traditional hardware-managed memory hierarchies.

As Autonomous Vehicles (AVs) become more common in the market, the development of new technologies and solutions for them advances quickly. However, there still are safety concerns regarding the increasing presence of AVs on public roads.For example, the California Department of Motor Vehicles reported an approximate average of 3 disengagement events for each AV under test in 2021 and 1 event for every 1,500 driven miles. Considering that a vehicle drives, on average, 15,000 miles per year, an AV would have ten such incidents annually. With this in mind, work needs to be done to enable AVs to handle unexpected situations (i.e., emergent behaviors) that can arise while driving, increasing the safety for both humans and AVs on the road. This dissertation discusses possible approaches to improve the detection and reasoning of emergent behaviors at runtime.

First, it describes SAFER, a framework to monitor individual systems using runtime verification alongside machine learning anomaly detection to detect emergent behaviors at runtime. SAFER achieves an average F1-score of 83% over four different example systems, showcasing its efficacy to be on par with related work while being applicable to different classes of applications. Next, it discusses DRIVE, a framework for monitoring collective systems that can work together to find global anomalies that affect collective safety by identifying violations in local properties. Throughout a state-of-the-art inspired truck platooning case study, DRIVE can detect all safety property violations, with most queries resolved under 1 ms and a maximum latency of 11 ms per query, demonstrating its promise. Lastly, it presents LOCoCAT, a low-overhead framework for emergent behavior reasoning to classify anomaly types based on vehicular data. LOCoCAT achieves an F1-score of up to 99.16% within the first 50 ms of the anomaly, allowing the system to react quickly. These three techniques can be combined to allow future AVs to operate more safely on the road.

We present High-Level Library Mapping, a technique that synthesizes a source memory module from a library of target memory modules. In this report, we define the problem of high-level library mapping for memories, identify and solve the three subproblems associated with this task and finally combine these solutions into a suite of two memory mapping algorithms. Experimental results on a number of memory-intensive designs demonstrate that our memory mapping approach generates a wide variety of cost-effective designs, often counter-intuitive ones, based on a user-given cost function, the target library and the mapping algorithm used.

Emerging mobile SoCs are increasingly incorporating heterogeneity in order to provide energy-efficiency while meeting performance requirements. Effective exploitation of power-performance tradeoffs in heterogeneous many-core platforms (HMPs), however, requires intelligent management at different layers, in particular at the operating system level. Operating systems need to continuously analyze the application behavior and find a proper answer for questions such as: What is the most power efficient core type to execute the application without violating its performance requirements? or Which option is more power-efficient for the current application: an out-of-order core at a lower frequency or an inorder core at a higher frequency? Unfortunately, existing operating systems do not offer mechanisms to properly address these questions and therefore are unable to fully exploit architectural heterogeneity for scalable energy-efficient execution of dynamic workloads.

In this thesis we present our vision of a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software. The general idea of reflection is to change your actions based on both external feedback and introspection (i.e., self-assessment). From a system perspective, this translates into performing resource management actuation considering both sensing information (e.g., readings from performance counters, power sensors, etc.) to assess the current system state, as well as models to predict the behavior of the system before performing an action. In this context, this thesis makes the following contributions:

• It describes MARS, a Middleware for Adaptive Reflective computer Systems. MARS consists of a toolchain for creating resource managers that allows users to easily compose models and policies that interact in a hierarchy defined by the granularity of the actuations performed in the system. MARS is implemented and evaluated on top a real Linux-based platform. Furthermore, MARS also provides an offline simulation infrastructure for fast prototyping of policies and large-scale or long-term policy evaluation.

• It proposes a performance/power modeling approach for HMPs which takes into account the effect of both microarchitecture-level components as well as system-level components such as the operating scheduler.

• It proposes a runtime task mapping approach for energy efficient HMPs. Energy efficient task-to-core mapping is done by combining on-chip sensor data and models of the underlying operating systems components implemented within MARS. It achieves average energy reductions of 23% when compared to the state-of-art task mapping techniques, while achieving similar performance.

• It proposes aging models to provide reliability-aware task-mapping for mobile HMPs. These contributions have shown that the extensive use of models to predict how the system will react to actuations is a promising scheme to pave the path towards more energy efficient heterogeneous systems. In this context, a framework which enables reflective resource management is an important building block to tackle the growing complexity of battery-powered devices.

This report discusses the model and input language for EXTEND, a synthesis system that permits extensible register transfer synthesis. EXTEND-L fills the need for a language that bridges the gap between existing behavioral input descriptions, which are too abstract, and structural schematics, which cannot capture the high-level behavior. The report first discusses previous work in behavioral synthesis and summarizes the deficiencies of these behavioral specifications. The report then describes the proposed langauge in detail, and concludes with a few examples that show its utility.

This paper discusses issues in benchmarking for synthesis, and suggests techniques for the comparison of benchmark descriptions, the synthesis tools used, as well as the synthesized designs finally generated. We propose a classification scheme for the assumptions made for the comparison of different synthesis tools, and present an Assumptions Chart that can be used to visualize different benchmarks, tools and synthesis results. We illustrate application of this Assumptions Chart using synthesis experiments that were conducted on some sample High-Level Synthesis Workshop bench-marks.