A 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm2, is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5~\mu \text{V}$ -rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

A 256-channel readout application specific integrated circuit (ASIC) called the very low-noise analog sampling engine (VASE) intended for the readout of column-parallel charge-coupled devices (CP-CCDs), is presented. Each channel uses a charge-sensitive amplifier and a first-order dual-gain sigma-delta analog-to-digital converter (ADC) that act as the front end of an extended counting ADC. The extended counting ADC directly implements correlated multiple-sampling as part of its operation. To reduce the noise due to input capacitance and to ensure a compact camera, the VASE input bonding pads are pitch matched to the CP-CCD to allow chip-to-chip bonding with minimal parasitic capacitance. The chip is designed in a modular way with each 16 input channels sharing a single differential analog output and digital serializer. VASE, with a die area of 38.1 mm2 and fabricated in 180-nm CMOS technology, achieves 22 e- equivalent noise charge (ENC) and a dynamic range of 190 ke- (78.7 dB) at a 4-MHz pixel rate (corresponding to a frame rate of 32 kfps when a 256 × 256 pixel sensor is read out on both sides) while dissipating 10.1 mW per channel. The prototype has been used to successfully image X-ray diffraction at a soft X-ray synchrotron.