High electron mobility III-V compound semiconductors such as indium arsenide (InAs) are promising candidates for future active channel materials of electron devices to further enhance device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been studied, combining the high mobility of III-V semiconductors and the well-established, low cost processing of Si technology. However, one of the primary challenges of III-V device fabrication is controllable, post-growth dopant profiling. Here InAs nanowires and ultrathin layers (nanoribbons) on SiO2/Si are investigated as the channel material for high performance field-effect transistors (FETs) and post-growth, patterned doping techniques are demonstrated.

First, the synthesis of crystalline InAs nanowires with high yield and tunable diameters by using Ni nanoparticles as the catalyst material on SiO2/Si substrates is demonstrated. The back-gated InAs nanowire FETs have electron field-effect mobilities of ~4,000 cm2/Vs and ION/IOFF ~104. The uniformity of the InAs nanowires is demonstrated by large-scale assembly of parallel arrays of nanowires (~400 nanowires) on SiO2/Si substrates by a contact printing process. This enables high performance, "printable" transistors with 5-10 mA ON currents.

Second, an epitaxial transfer method for the integration of ultrathin layers of single-crystalline InAs on SiO2/Si substrates is demonstrated. As a parallel to silicon-on-insulator (SOI) technology, the abbreviation "XOI" is used to represent this compound semiconductor-on-insulator platform. A high quality InAs/dielectric interface is obtained by the use of a thermally grown interfacial InAsOx layer (~1 nm thick). Top-gated FETs exhibit a peak transconductance of ~1.6 mS/µm at VDS=0.5V with ION/IOFF >104and subthreshold swings of 107-150 mV/decade for a channel length of ~0.5 µm.

Next, temperature-dependent I-V and C-V studies of single InAs nanowire FETs are utilized to investigate the intrinsic electron transport properties as a function of nanowire radius. From C-V characterization, the densities of thermally-activated fixed charges and trap states on the surface of as-grown (unpassivated) nanowires are investigated to allow the accurate measurement of the gate oxide capacitance. This allows the direct assessment of the electron field-effect mobility. The field-effect mobility is found to monotonically decrease as the radius is reduced to sub-10 nm, with the low temperature transport data highlighting the impact of surface roughness scattering on the mobility degradation for smaller radius nanowires. Next, the electrical properties of the InAs XOI transistors are studied, showing the critical role of quantum confinement in the transport properties of ultrathin XOI layers.

Following the investigation of the electrical properties of undoped InAs nanostructures, post-growth, surface doping processes for InAs nanostructures are addressed. Nanoscale, sulfur doping of InAs planar substrates with high dopant areal dose and uniformity by using a self-limiting monolayer doping approach is demonstrated as a means to create ultrashallow junctions. From transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), a dopant profile abruptness of ~3.5 nm/decade is observed without significant lattice damage. The n+/p+ junctions fabricated using this doping method exhibit negative differential resistance (NDR) behavior, demonstrating the utility of this approach for device fabrication with high electrically active sulfur concentrations of ~8x1018 cm-3.

Next, a gas phase doping approach for InAs nanowires and ultrathin XOI layers using zinc is demonstrated as an effective means for enabling post-growth dopant profiling of nanostructures. The versatility of the approach is demonstrated by the fabrication of gated diodes and p-MOSFETs. Electrically active zinc concentrations of ~1x1019 cm-3 are achieved which is necessary for compensating the high electron concentration at the surface of InAs to enable heavily p-doped structures. This work could have important applications for the fabrication of planar and non-planar devices based on InAs and other III-V nanostructures which are not compatible with conventional ion implantation processes that often cause severe lattice damage and local stoichiometry imbalance.

Lastly, an ultrathin body InAs XOI tunneling field-effect transistor (TFET) on Si substrate is demonstrated. The post-growth, zinc surface doping approach is used for the formation of a p+ source contact which minimizes lattice damage to the ultrathin body InAs XOI compared to ion implantation. The transistor exhibits gated NDR behavior under forward bias, confirming the tunneling operation of the device. In this device architecture, the ON current is dominated by vertical band-to-band tunneling and is thereby less sensitive to the junction abruptness. This work presents a device and materials platform for studying III-V tunnel transistors.