We present a design exploration strategy for the beamformer system, an example of a typical DSP system. In order to do so, we first define a parameterized design template for the beamformer and for a FIR filter, since the filtering operation is a part of the overall beamformer system. We then discuss some approaches for varying the design parameters for the filter and the beamformer system, under constraints imposed by technology or the designer.

In this report, we present an architectural classification based on four design features: customization, slicing direction, parallelism and pipelining. We also propose a strategy for exploring the architectural space of a design by varying these design features in a systematic way. We believe that design exploration carried out in such a manner will not only save considerable designer time and effort but also result in more cost-effective designs. In order to demonstrate the effectiveness of our exploration strategy we give the results of applying it on four examples: a timer system, an FIR filter, an FFT datapath, and a robot kinematics system.

We present a specification of a general environment for behavioral synthesis centered around the user/designer as the primary motivator for decisions in design development. At each stage of the design process, the user can perform transformations on the design description through graphical user interfaces. Quality measures, physical estimates, and design hints are given to the user at each stage.

When synthesizing a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be specified in multiples of a clock cycle. In the absence of any tool to guide the selection of a clock cycle, a bad choice of the clock period could adversely affect the performance of the synthesized design. We present an algorithm for estimating the system clock based on a clock wastage minimization criteria. Limitations of previous approaches to the problem are discussed. The results obtained prove that the clock cycle estimated by the Clock Wastage Minimization method produce faster designs than previous solutions to the problem.

This work describes an integrated design methodology focusing on power exploration at behavioral level. We present a behavioral-level tool for architecture selection and power estimation within the SpecSyn [GVNG94] environment. The implementation has two major steps of scheduling and power estimation. Power analysis is done in both steps; it is approximate in the former and detailed in the latter. A combination of empirical and analytical approaches is used for power estimation. We provide several case studies of common benchmarks to illustrate the design methodology as also its interactive and efficient nature that enables fuller design space exploration. We evaluate power versus performance trade-offs for different implementations of each example, using our tool. An important premise for this work is accurate characterisation of resource library for power.

The use of a realistic component library with multiple implementations of operators, results in cost efficient designs; slow components can then be used on non-critical paths and the more expensive components on only the critical paths. This report presents a cost-optimized algorithm for selecting components and pipelining a data flow graph, given a multiple-implementation library, and throughput and latency constraints. Results on several DSP examples indicate the importance of component selection as a parameter in design space exploration.

In the past, the research on representation for synthesis systems had been focusing on two main issues, the completeness and the efficiency. There is, however, another important issue that is not addressed by most of traditional representation, the uniqueness. This report proposes a representation for synthesis called the Assignment Decision Diagram (ADD) that is complete, efficient and partially unique. In addition, the ADD can enrich the results of the synthesis. Discussion of ADD's properties and its uses in synthesis is provided in this report.

Scheduling estimation in system level design plays an important role in estimating design metrics of a hardware implementation. Moreover, accurate estimates based on a realistic design model are usually expected. In this report, we present techniques for scheduling estimations based on a control/datapath pipelining architecture. Schedules are computed under both resource and architectural constraints. The resource allocation includes not only functional units but also storage and communication units. Our techniques enable designers to obtain fast and accurate estimates of scheduling.

The Discrete Cosine IVansform (DCT) is used in the MPEG and JPEG compression standards. Thus, the DCT component has stringent timing requirements. The high performance which is required cannot be achieved by a sequential implementation of the algorithm. In this report, we explore different optimization techniques to improve the performance of the DCT. We discuss various pipelining options to further reduce the latency. We present a transformation of the algorithm that reduces the memory requirements and hence, reduces the cost of the implementation. We also describe RT-level implementations of the sequential, pipelined and memory optimized designs.