The power consumption of next-generation high-performance processors is expected to reach and eventually exceed 1000 W, with core logic voltages below 1 V and peak current demand beyond 1000 A. To deliver ultra-high currents at low voltages with minimal power distribution network losses, this paper presents a compact 48-V-to-sub-1-V switching bus converter (SBC), a single-stage hybrid switched-capacitor (SC) voltage regulator for processor vertical power delivery (VPD). The SBC comprises a 2-to-1 SC front-end and two 10-branch series-capacitor buck modules, which are merged through two switching buses. A hardware prototype was designed and built with two-phase coupled inductors for performance validation. The coupled inductors were customized for VPD, with their windings both functioning as part of the coupled inductors and serving as the connection between the SBC and the processor motherboard. The hardware prototype met a stringent maximum height limit of 5 mm and achieved a current density of 0.614 A/mm2 at a full-load current of 600 A. Additionally, it demonstrated excellent performance compared to the state-of-the-art academic works for 48 V to point-of-load conversion.

For the Phase-II Upgrade of the ATLAS Detector [1], its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100% silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: An early program using readout chips designed using a 250 nm fabrication process (ABCN-250) [2,2] and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.

During the Laser Interferometer Gravitational-wave Observatory and Virgo joint science runs in 2009-2010, gravitational wave (GW) data from three interferometer detectors were analyzed within minutes to select GW candidate events and infer their apparent sky positions. Target coordinates were transmitted to several telescopes for follow-up observations aimed at the detection of an associated optical transient. Images were obtained for eight such GW candidates. We present the methods used to analyze the image data as well as the transient search results. No optical transient was identified with a convincing association with any of these candidates, and none of the GW triggers showed strong evidence for being astrophysical in nature. We compare the sensitivities of these observations to several model light curves from possible sources of interest, and discuss prospects for future joint GW-optical observations of this type. © 2014. The American Astronomical Society. All rights reserved.