As the physical dimensions of the MOSFET have been scaling, the supply voltage has not scaled accordingly and thus the power density has been continuously increasing. This is mainly due to the fact that transistor operation requires carriers to go over the source side potential barrier which limits the subthreshold swing of a MOSFET to 60mV/dec at room temperature and thus inhibits the scaling of the threshold voltage. Tunneling devices utilizing the band-to-band tunneling mechanism have been known to overcome this fundamental limit.

In this thesis, the tunneling field-effect-transistor (TFET) is explored to replace conventional MOSFETs for low power applications. The band-to-band tunneling mechanism is looked into in order to develop a more accurate tunneling model that considers the change in effective mass during the transition between the conduction and valence band. Device simulator parameters are modified with this model and are used in designing the TFET. The silicon P-I-N structure TFET is studied through simulation and various experimental splits as a baseline for the TFET development. High tunneling currents are measured from a short channel device with a flash and spike anneal combination and a novel silicided source TFET using silicide induced dopant segregation is shown to achieve sub-60mV/dec subthreshold swing. Measurement and analysis methods of the transistor current and subthreshold swing to verify the TFET are discussed. Lower band gap Ge devices and Strained Si/Ge hetero-structure devices utilizing a lower effective bandgap are also explored to improve the performance of the TFET.

Scaling of supply voltage V_dd has significantly slowed down since the 130 nm node. As a result, integrated circuit (IC) power consumption has been on the rapid rise. This presents a serious thermal management challenge and potential limiter of integration density as well as a rapidly growing portion of the world electricity demand. The problem lies in the 60 mV/dec swing limitation of any device involving charge flow over energy barrier (i.e., current state of art CMOS). This requires at least 60 mV to decrease the transistor current by 10X. The future low power or "green" energy efficient scenario would benefit from a device that is friendlier to V_dd scaling. A transistor where carriers tunnel through rather than flow over a barrier is not subject to this limitation. However, achieving sub 60 mV/dec at current ranges of interest and over many decades is not trivial when relying solely on transmission probability modulation (i.e., increase/decrease of tunnel barrier width). Instead, if the absence/presence of tunneling state overlap is exploited a sharp "off" to "on" transition is achievable. By engineering the transistor device structure such that this overlap (i.e., onset of tunneling) occurs in a region of high electric field results in steep sub 60 mV/dec response over many decades of current. One novel design utilizes heavily doped, ultra shallow N+/P+ junctions to achieve this "sudden tunneling overlap" effect. Another design involves use of ultra thin body silicon-on-insulator (5 nm) to achieve a similar effect. Simulation results show sub 500 mV V_dd is possible if suitable low-E_g material is introduced. Both designs have been fabricated in silicon and their measurement results are presented.

With the scaling of the transistor, fabrication of an actual device and modeling of an ultra-short channel transistor becomes more and more challenging. Dr. Salahuddin proposed a negative capacitance field-effect transistor (NCFET) in 2008. By utilizing the ferroelectric negative capacitance region with proper capacitance matching a ferroelectric layer with a dielectric layer, the overall effective oxide thickness could be further thinned down without affecting much of the carrier mobility.A technique of optimization of an NCFET will be proposed in chapter 2. By utilizing process techniques like mask oxidation, a non-uniform interfacial layer can be formed to create a more uniform metal-oxide-semiconductor capacitance along the channel (Cmos). The overall capacitance matching of an NCFET can be improved because of a uniform Cmos profile. Chapter 3 will introduce a simulation scheme of NCFETs variation due to dielectric grains within a ferroelectric film. This scheme can be applied to the future estimation of NCFETs variation given the grains' size and the ferroelectric parameters. The effect and compact modeling of the polarization gradient effect will be demonstrated in Chapter 4. With the feature of polarization gradient effect in an NCFET compact model, the characteristics of an NCFET can be better captured, such as negative drain resistance and negative drain-induce barrier 2 effect (DIBL). Energy analysis of an NCFET will be presented in Chapter 5. The consistency between TCAD energy calculation by the integral over the grids with the Landau equation and power consumption calculation from the circuit is shown in detail. Negative capacitance benefits on FinFET and gate-all-around (GAA) FET will be presented in chapters 6 & 7, respectively. Baseline devices of a FinFET and a GAAFET are made in technology computer-aided design (TCAD) and are calibrated to International Roadmap for Devices and Systems (IRDS) tables. NC parameters are also extracted from an experiment on metal-oxide-semiconductor capacitance (MOSCAP). How many nodes NC extends the baseline will be discussed. A compact model of an anti-ferroelectric on an NCFET will be presented in Chapter 8. Potential applications of machine learning will be illustrated in Chapters 9 & 10. Machine learning-assisted parameter extraction will be presented in Chapter 9. In the long run, using machine learning-assisted models as an alternative to the conventional equation-based compact models will be shown in Chapter 10. In the end, Chapter 11 will conclude chapters and propose some future work.

Compact model plays an important role in designing integrated circuits and serves as a bridge to share the information between foundries and circuit designers. Since various flavors of transistor architectures like FDSOIs and FinFETs are proposed to improve device performances, the accurate, fast, and robust compact models, which are capable of reproducing the very complicated transistor characteristics like transconductance, are urgently required. Novel device concept, such as tunnel FETs (TFETs) and negative capacitance FETs (NCFETs), needs new device modeling methodology and understanding of device physics. In addition to transistors, memory device like magnetic tunnel junction (MTJ) compact model is also crucial for circuit designs. This dissertation presented the advanced research on compact models for the state-of-the art transistor and memory technologies: FDSOIs, FinFETs, TFETs, NCFETs, and MTJs.

Due to the limitations in the aggressively scaled planar transistors, the devices with good electrostatic control are discussed and modeled into the industry standard model - BSIM-IMG for FDSOIs and BSIM-CMG for multi-gate FETs. Although the dynamic back-gate bias change help reduce the static power in FDSOIs, the leakages, overlap capacitance, and carrier transport are thus showing back-gate bias-dependence. The enhanced gate-related leakage, overlap capacitance, and mobility compact models are validated against the silicon data and incorporated into BSIM-IMG. The leakages through subsurface path and source-to-drain direct tunneling due to extremely short channel are also included in this work, which are in excellent agreement with the technology computer-aided design (TCAD) and atomistic simulations. The computationally efficiency of these models are the key solutions for evaluating the circuit performance of future technology nodes.

Two paradigms of steep subthreshold slope transistors - TFETs and NCFETs as the promising candidates for future Internet of Things (IoT) and logic/analog applications are also presented in this thesis. TFET has a gated p-i-n diode structure, where the current relies on direct band-to-band tunneling in source/channel junction. Such tunneling mechanism breaks the tradition limitation of MOSFET turn-ON characteristics called the Boltzmann tyranny. The improvements in power consumption and delay of circuits are thus the emphasis and attention of device community, where the need of TFET compact model is fulfilled with the developed model in this work. NCFET is rapidly emerging as a preferred replacement for traditional MOSFET since the recent discovery of ferroelectric (FE) materials to amplify the voltage suggests that further scaling supply voltage is possible with the CMOS-compatible fabrication process of NCFET. The short channel effect, ferroelectric variability, and spacer optimization design are the focus in this thesis. The compact model of NCFET is improved to be more predictive for ferroelectric properties with verification against TCAD simulations. Monte-Carlo method is carried out in FE variability study, where the main finding is that the dielectric phase is critical but fortunately is theoretically possible to be absent. The spacer design reveals that further engineering the capacitance matching via parasitic capacitance is the key solution for future technology nodes.

In addition to transistor compact models and physics, the memory device - spin-transfer-torque magnetic tunnel junction (STT-MTJ) is also presented. The resistances and critical currents are derived from the Landau-Lifshitz-Gilbert (LLG) equation and modeled analytically. The RC sub-circuit is found to describe the dynamic switching behavior of MTJ due to the precession and thermal fluctuation. The proposed MTJ compact model has been validated with silicon data from the industry and is capable of simulating a memory circuit with previously mentioned BSIM models.

As scaling continues, the number of transistors per unit area and power density are both on the rise. A reduction in V_dd is highly desirable to reduce power consumption. For MOSFETs however, this would mean scaling the threshold voltage to maintain performance and thereby enhancing the off current and static power consumption since MOSFETs are limited to a swing of 60mV/decade at best. A low voltage transistor that allows V_dd scaling to 0.5V and below is highly desirable.

In this thesis, gate induced band-to-band tunneling transistors are explored as a low voltage alternative because of their potential to achieve lower than 60mV/decade turn-off. Since BTBT is strongly dependant on the band gap of the semiconductor, moving from Silicon to Germanium to lower band gap materials can help scale ,V_dd. Biaxially strained Si_1-xGe_x based heterostructures can provide ultra low effective band gaps. Strain is used to engineer complimentary Si_1-xGe_x heterostructures with low effective band gap for both N and P type transistors. The design and fabrication of heterostructure based tunnel transistors is explored to help scale V_dd to 0.5V and below. Dopant engineering techniques to enhance the electric field are also explored both with simulations and experiments.

Multiple-gate MOSFETs with superior short channel control are expected to replace planar CMOS in the near future. An accurate and computationally efficient compact transistor model is necessary to simulate circuits in multiple-gate MOSFET technologies. In this dissertation research, a compact multiple-gate MOSFET model, BSIM-MG is developed. BSIM-MG includes independent multi-gate compact model BSIM-IMG and common multi-gate compact model BSIM-CMG. We focus on BSIM-IMG for multiple-gate MOSFETs with independent front- and back-gates. The basic formulations for surface potential, drain current and charge are derived and verified against TCAD simulations with excellent agreements. The model preserves important property of multi-gate MOSFETs such as volume inversion. Non-ideal effects including short channel effects, length dependent back-gate coupling, transport models, leakage currents, parasitic resistances and capacitances, temperature effects and self heating are considered in the model. The model expressions are carefully formulated so that the symmetry of the source and drain is preserved. Rules for maintaining symmetry are discussed in this dissertation.

For the common multi-gate transistor model BSIM-CMG, the basic expressions have been improved so that it is compatible with a novel non quasi-static effects modeling technique — charge segmentation. In addition, a parasitic source/drain resistance model is developed, including three components: the contact resistance, the spreading resistance, and the bias-dependent extension resistance. Both BSIM-CMG and BSIM-IMG models are verified against TCAD and measured data.

The use of the FinFET compact model to model manufacturing variation in a FinFET technology is further explored. The model matches measured data well for both the nominal case and the statistical distribution for NMOS threshold voltage as well as the read static noise margin. A non-Gaussian threshold voltage distribution is observed for nFET devices, and the compact model successfully captures the distribution. We further outlined and demonstrated a Monte-Carlo based procedure for designing FinFET SRAM cells using the extracted variation information.

Technology scaling has enabled numerous CMOS analog circuits for low cost radio-frequency applications. The modeling of MOSFET thermal noise becomes very important. In the final part of this dissertation research, a new thermal noise model is developed for the industry standard BSIM4 model that enhances the existing thermal noise formulation in BSIM4. The model is verified against a segmented channel MOSFET model as well as measured data. It is implemented in Berkeley SPICE3 and is ready for industry use. A method to port the model to BSIM-MG for thermal noise modeling in multi-gate MOSFETs is also presented.

Mathematical compact models play a key role in designing integrated circuits. They serve as a medium of information exchange between foundries and designers. A compact model, which is a set of long mathematical equations based on the physics of each transistor, is capable of reproducing the very complex transistor characteristics in an accurately, fast, and robust manner. This dissertation presents the latest research on compact models for advanced transistor technologies: FinFETs, Ultra-thin body SOIs (UTBSOIs), Gate-All-Around (GAA) FETs, and Negative Capacitance (NC) FETs.

Since traditional transistor scaling had reached limitations due short-channel effects and oxide tunneling, the introduction of FinFET and UTBSOIs in high-volume manufacturing at 20nm, 14nm and 10nm technology nodes had let the electronic industry to keep obtaining performance and density advantages in technology scaling. For smaller nodes such as 5nm, and 3nm, GAA FETs transistors are expected to replace traditional transistors. Production ready compact model for current and future FinFETs are presented in this thesis. The Unified Compact Model can model FinFETs with realistic fin shapes including rectangle, triangle, circle and any shape in between. A new quantum effects model will also be presented, it enables accurate modeling of III-V FinFETs. Shape agnostic short-channel effect model for aggressive $L_G$ scaling and body bias model for FinFETs on bulk substrates are also included in this work. This computationally efficient model is an ideal turn-key solution for simulation and design of future heterogeneous circuits.

For extremely scaled technologies, NC-FETs are quickly emerging as preferred candidates for digital and analog applications. The recent discovery of ferroelectric (FE) materials using conventional CMOS fabrication technology has led to the first demonstrations of FE based NC-FETs. The ferroelectric material layer added over the transistor gate insulator help in several device aspects, it suppress short-channel effects, increase on-current due voltage amplification, increase output resistance in short-channel devices, etc. These exciting characteristics has created an urgency for analysis and understanding of device operation and circuit performance, where numerical simulation and compact models are playing a key role.

This thesis gives insights into the device physics and behavior of FE based negative capacitance FinFETs (NC-FinFETs) by presenting numerical simulations, compact models, and circuit evaluation of these devices. NC-FinFETs may have a floating metal between FE and the dielectric layers, where a lumped charge model represents such a device. For a NC-FinFET without a floating metal, the distributed charge model should be used, and at each point in the channel the FE layer will impact the local channel charge. This distributed effect has important implications on device characteristics. These device differences are explained using numerical simulation and correctly captured by the proposed compact models. The presented compact models have been implemented in commercial circuit simulators for exploring circuits based on NC-FinFET technology. Circuit simulations show that a quasi-adiabatic mechanism of the ferroelectric layer in the NC-FinFET recovers part of the energy during the switching process of transistors, helping to minimize the energy losses of the wasteful energy dissipation nature of conventional transistor circuits. As circuit load capacitances further increase, $V_{DD}$ scaling becomes more dominant on energy reduction of NC-FinFET based circuits.

The semiconductor industry has relied on accurate device models for analyzing, predicting and innovating integrated circuit design. Multi-gate MOSFET device architectures like FinFETs are beginning to replace their planar MOSFET counterparts at the 22nm technology node to enable continued technology scaling. Vertical cylindrical gate (CG) MOSFET are touted to replace planar MOSFETs as the memory device for DRAM and NAND Flash offering increased area density. New device architectures together with relentless scaling of MOSFETs for performance mean increased complexity and new device physics that need to be comprehended. This new understanding needs to be translated into device models for technology progress. Newer device models also require newer methodologies for model creation process and usage for circuit design.

In this thesis we develop a comprehensive compact SPICE model for a CG MOSFET. Relying on fundamental physics based electrostatics description (Poisson Equation) of the device analytic equations for terminal current and capacitance are derived forming the core model. Including all requisite real device effects we validate this model to both numerical simulations (TCAD) and hardware silicon data showing < 1% RMS error when the model is tuned to the data. For channel diameters < 20nm quantum mechanical confinement effects tend to dominate. The complex bias and geometry dependence of the inversion charge centroid is captured through a phenomenological model. This model helps accurate prediction of the reduction in gate capacitance of a CG MOSFET. This model was also extended to carrier confinement in thin channels such as the double gate FET or FinFET. The vertical CG MOSFET exhibits asymmetry w.r.t. source and drain. With the aid of TCAD we propose that non-uniform vertical channel doping and structural differences in the top and bottom (source/drain) junction regions as the major contributors to the asymmetric behavior. We then create a mathematical framework to capture these asymmetries in the compact model developed above. We validate this approach by showing excellent agreement to hardware silicon data from a high voltage vertical CG MOSFET technology. All these models have been incorporated in BSIM-CMG the first industry standard multi-gate MOSFET model. Despite including many complex physical effects the resultant model can be executed in the order of few 10's of secs (per operating point) enabling rapid very large scale integrated circuit design.

A compact SPICE model maintains a balance of predictive nature and flexibility with many sub-components describing various physics and tunable parameters in order to capture data from various sources accurately. This could quickly become unmanageable during a model creation process. For this we propose a RF model extraction procedure that does not require any additional sub-circuit elements and takes advantage of advances in parameter optimization tools available today in an efficient manner. We demonstrate this procedure on high frequency data from multiple planar MOSFET technologies discussing various use cases. Using BSIM6, a bulk planar MOSFET compact model the resultant procedure was able to capture silicon data even beyond the cut-off frequency of the MOSFET and predict various RF circuit design figure of merits with great accuracy.

In the last couple decades, the phenomenal growth of mobile electronics is fueling the

demand for multi-functional, high performance and ultra-low power integrated circuits.

Reduction in Vdd to achieve orders of magnitude reduction of energy consumption is crucial if the promise of many more decades of growth of electronics usage is to be realized. For MOSFETs, Vdd reduction can only be achieved at the expense of speed loss and/or off-state leakage increase because the subthreshold slope is fundamentally limited to 60mV/decade. New transistors with sub-60mV/dec swing allowing Vdd scaling to 0.3V and below are therefore highly desirable.

In this research, two approaches to achieve transistors with sub-60mV/dec swing are

explored. Feedback FET (FBFET) uses positive feedback to induce an abrupt change in current with a small change in the gate voltage. Experimental results show FBFET can achieve less than 2mV/dec swing, with Ion/Ioff ratio larger than six-orders-of-magnitude. Simulation is used to illustrate the operating principle, and to evaluate the potential of FBFET. Another approach is to integrate negative capacitance element onto the gate stack of MOSFETs. The negative capacitance does not change the transport physics, but rather seeks to "amplify" the gate voltage electrostatically to achieve less than 60mV/dec swing. Design considerations and optimizations of Negative Capacitance FET (NCFET) are explored using simulations. Simulation shows the possibility of achieving hysteresis free, sub-30mV/dec operation of NCFET based on an UTBSOI design. The experimental NCFET result of epitaxial ferroelectric thin film on SOI substrate is presented.

Scaling transistors is good for speed but scaling interconnect degrades it due to resistances and parasitic capacitances. Scaling of supply voltage VDD has significantly slowed down since the 130 nm node. As a result, integrated circuit (IC) power consumption has been on the rapid rise. Crosstalk noise problem has been also increased as scaling. Reducing capacitance is an excellent solution for these problems; the circuit delay, power consumption, and crosstalk noise. The future transistor and interconnect with lower capacitance should be considered to overcome these problems. An air-gap structure can be attractive solution for both transistor and interconnect. Novel air-gap structures are proposed in this research. In the transistors, the conventional spacer structure is replaced with air-gap spacer structure. This new structure leads for the fringing capacitance to be decreased much. Therefore, the speed and power consumption can be improved. This structure can be compatible with both the conventional gate-first and gate-last process. Other designs involve use of self-aligned contact or linear contact processes to achieve a much more effect. The low-k spacer transistor which is included this air-gap spacer transistor degrades the current performance. Thus, the air-gap spacer technology is very helpful to the high performance devices but it is not much helpful to the low stand-by power devices. The corner spacer transistor with high-k inner spacer and low-k outer spacer is proposed to overcome the degradation of current performance. The high-k material can improve the current performance and the low-k material can improve the capacitance. In the interconnects, the proposed novel air-gap interconnects are compatible with both the subtractive etch interconnect and dual damascene interconnect. These air-gap structures can improve not only the effective dielectric constant but also crosstalk noise problem.