In this report, issues related to design descriptions are discussed. Several existing description styles including timing diagrams, algorithmic-state-machine charts, state-action tables, VHDL, SpecCharts, and signal-flow graphs are investigated, and their features are compared. Five examples (addressed handshake read protocol, parallel counters, controlled counter, finite-impulse-response (FIR) filter, anda simple computer system) described in different styles are also presented.

Due to the recent increases in design complexity, behavioral synthesis has become an important area of research and company interest. However, there has been market resistance to accepting the automatic behavioral synthesis approach as a practical solution in general because, first, it often produces results inferior to manual designs, and second, it allows only minimum user control. To develop a feasible approach for behavioral synthesis to overcome the hurdles faced by the automatic approach, we propose interactive behavioral synthesis, which attempts to maximally utilize the human designer's insights. Using interactive behavioral synthesis, the users can control the design process, observe the effects of design decisions, and manually override synthesis algorithms at will. In this report, we present a design methodology as how the user interacts with an interactive behavioral synthesis system, which in contrast to an automatic synthesis system, enables the human designer fine-grain control over each synthesis task and continually supplies feedback in the form of quality measures so that the user can make informed design-related decisions. To demonstrate the proposed design methodology, we also present in this report a walk-through square-root approximation (SRA) example.

In interactive behavioral synthesis, the designer can control the design process at every stage, including modifying the schedule of the design to improve its performance. In this report, we present a methodology for performance optimization in interactive behavioral synthesis. Also proposed in this report are several quality metrics and hints that can assist the user in utilizing the proposed methodology. When the user is optimizing the performance of the design, one important decision is the selection of a clock period. We have developed an algorihm to estimate the effect of different clock periods on the execution time of the design. This algorithm can be used to facilitate clock period selection by the user in order to optimize the performance of the design. We have tested our methodology on several benchmarks. The experimental results support the proposed methodology on several benchmarks. The experimental results support the proposed methodology by demonstrating an average improvement of 46.2% in design performance.

In order to reduce the design cost of pipelined systems, resources may be shared by operations within and across different pipe stages. In order to maximize resource sharing, a crucial decision is the selection of a clock period, since a bad choice can adversely affect the performance and cost of the design. In this report, we present an algorithm to select a clock period that attempts to minimize design area while satisfying a given throughput constraint. Experimental results on several examples demonstrate the quality of our selection algorithm and the benefit of allowing resource sharing across pipe stages.

Identifying mutual exclusiveness between operators during behavioral synthesis is important in order to reduce the required number of control steps or hardware resources. The quality of the synthesized design is strongly influenced by the number of mutually exclusive operators that can be identified by synthesis algorithms. To improve the quality of the design, we propose a representation, the Condition Graph, and an algorithm for comprehensive identification of mutually exclusive operators. Previous research efforts have concentrated on identifying mutual exclusiveness by examining language constructs such as IF-THEN-ELSE statements. Thus, their results heavily depend on the description styles. The proposed approach can produce results independent of description styles and identify more mutually exclusive operators than any previous approaches. The Condition Graph and the proposed algorithm can be used in any scheduling or binding algorithms. Experimental results on several benchmarks have shown the efficiency of the proposed representation and algorithm.

Due to recent increases in chip complexity, behavioral synthesis has become an important area of research and company interest. However, there has been market resistance to the automatic behavioral synthesis approach for two reasons. It often produces results inferior to manual designs, and it allows only minimal user control. To overcome these hurdles, we present a design methodology for human interaction in design synthesis, which, in contrast to the automatic synthesis approach, gives the human designer fine-grain control over synthesis tasks, and continually supplies feedback in the form of quality measures so that the user can make informed design-related decisions. To confirm the feasibility of the proposed design methodology and to demonstrate its power and flexibility, we also present the Interactive Synthesis Environment (ISE), a working software environment comprising design views, quality measure feedback, and synthesis algorithms.

In this report, we present a top-down VHDL modeling technique which consists of two main modeling levels: specification level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and effectiveness of this methodology. All models have been simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibilty of the modeling strategy and provide performance measures of RP design features.