Hyper-Dimensional computing (HDC) is a machine learning framework that has made in- roads in low-power edge-AI applications. With simple bitwise vector operations and a small memory footprint, HDC demonstrates improved energy-efficiency for biosensing classification tasks compared to conventional machine learning methods. Recent interest in HDC has developed complex algorithms that enable the use of HDC systems for cognitive reasoning and control applications. Although previous hardware for HDC achieve impressive energy- efficiency for certain tasks, they face several issues with the growing application space. This dissertation covers the goals, design, optimization, and implementation of an energy-efficient multipurpose processor for HDC.The first half of the dissertation overviews the recent expansion of HDC algorithms and the corresponding hardware to implement them efficiently. The shortcomings of previous hardware for HDC is analyzed and used to create goals for the Hyper-Dimensional Processing Unit (HPU), the first multipurpose HDC processor. The second half describes the physical realization and optimization of the HPU, characterized with two tape-outs. HPUv2 achieves an impressive energy-efficiency of 168 pJ per operation, making it competitive with previous application-specific hardware. The fabrication, verification, and characterization of the HPU architecture demonstrate the viability of an energy-efficient multipurpose processor that can enable intelligent HDC systems on the edge.