The continued push for microelectronics scaling has driven many changes in modern transistor design, such as the adoption of non-planar, multi-gate architectures (e.g., FinFETs) starting at the 22nm node. It is envisioned that other solutions such as junctionless FETs (JL-FETs), tunnel FETs (TFETs), or heterogeneous materials integration may be needed to sustain the pace of Moore’s law beyond 14nm. To assess the viability of these emerging devices prior to commercial investment, we must consider the impact of process variations such as line edge roughness (LER) and random dopant fluctuation (RDF), both of which are major concerns in the nanoscale regime. The challenges associated with dimensional scaling also compel us to explore heterogeneous integration as a possible end-of-roadmap solution for future micro- and nanoelectronics.

In this dissertation, we first present our findings on the impact of LER and RDF variability on FinFETs, JL-FETs, and TFETs targeted for sub-32nm generations. Using technology computer-aided design (TCAD) simulations combined with physical descriptions by which LER and RDF affect the intrinsic operation of different FETs, we compare the impact of LER and RDF on the emerging candidates of interest. We extend the study to include III-V FETs as well to determine if materials like InGaAs are inherently more or less affected by variability compared to equivalently designed silicon devices. Second, we study how heterogeneous integration (HGI) of different material systems can drive a new approach toward improving circuit and system performance outside of traditional scaling concepts. To this end, we develop a cross-layer evaluation framework (spanning process, device, and circuit-level perspectives) to assess the potential benefits of InGaAs/Ge-based HGI circuits against silicon-only technology. To give credence to the framework, we also present experimental work in developing a nanotransfer printing process to enable feature-level HGI in real-world settings. Third, we present a method to fabricate coplanar supercapacitors onto silicon substrates for integration with microelectronic circuits. Along with experimental demonstrations, we also develop a physical TCAD model to enable simulation-based design exploration and optimization of on-chip supercapacitors for integrated circuit applications.

Ultimately, the insights gained in this study will help guide the semiconductor industry to choose next-generation device technologies which are best suited for commercial adoption with process variability and the potential for heterogeneous integration in mind.