The vast applications of millimeter wave (mm-wave) and sub-terahertz (sub-THz) integrated circuits (ICs) has inspired significant interest and research into this technology. The available large bandwidths at these high frequencies enables high data rate wireless communication systems, high resolution radars, and high resolution imaging systems. Therefore, implementing low-cost, reliable, low-power, and low-size mm-wave and sub-THz systems can be a technological milestone which can create a lot of opportunities in academia and industry.
Challenges related to implementing mm-wave and sub-THz integrated circuits includes but not limited to low power generation capabilities of transistors at high frequencies, lossy passive elements, and high path loss. This work is focused on presenting novel architectures and methodologies to overcome these challenges in different applications of mm-wave and sub-THz systems.
First, a new two-element phase-locked loop (PLL)-coupled array for the implementation of mm-wave and sub-THz phased arrays is presented. This architecture avoids using lossy phase shifter to create the required phase shift between the adjacent elements in a phased-array system. The required phase shift is generated by utilizing a dual nested loop PLL. The two PLL loops work together to stabilize the frequency and create the required phase shift. Moreover, it can be scaledsimply by adding more unit cells to the architecture. A 112-121-GHz two-element phased array is designed and fabricated in a standard 65-nm CMOS process. It consumes 147-mW power and provides a phase shift of 46.7degrees ranging from 58.53 degrees to 105.2 degrees at 117 GHz.
Second, a new four-frequency-shift keying (4FSK) transceiver (TRX) at 145–185-GHz operation frequency is presented. The proposed non-coherent TRX is a fully integrated bit-in–bit-out communication system without the need for separate modulators/demodulators (modems). The transmitter (TX) core includes only one voltage-controlled oscillator (VCO), which can generate four different frequencies based on the two parallel streams of binary data at its input. The receiver (RX) with a frequency overlapping architecture demodulates the 4FSK signal and recovers the two parallel streams of binary data. Both the TX and the RX are designed and fabricated in a standard 65-nm CMOS process. The TX and RX consume 62- and 120-mW power, respectively. The highest achieved data rate is 17 Gb/s at an 18-cm link distance with 10.7-pJ/bit energy efficiency.
Third, a 110-mW 39-GHz Doppler radar front end in 65-nm CMOS for displacement and vibration sensing is proposed. This Doppler radar topology is proposed to achieve ultrahigh displacement range accuracy and sensitivity and to eliminate detection nulls without using quadrature demodulation. An edge-driven phase demodulator (EDPD) processes the rectified square-wave intermediate signal and converts displacement/vibration to a true-dc/baseband signal with a constant gain. Coherent demodulation and signal generation through common-referenced subsampling phase-locked loops (SSPLLs) allow the radar to achieve 4- µm static range accuracy and 39-nm vibrational (at 10 kHz) range sensitivity in measurement.