Scaling in silicon semiconductor process technology, although driven by digital applications, has also enabled the operation of analog integrated circuits (ICs) at higher and higher frequencies. Over the past 15-20 years, ICs operating at millimeter-wave (mm-Wave), the frequency range between 30 GHz and 300 GHz, have been demonstrated with increasing performance and complexity.

One important application for mm-Wave ICs has been in automotive radar, where they have been used to make accurate measurements of distance and velocity with minimal processing required. There also has been significant interest in adapting this technology for non-vehicular applications, such as gesture recognition, room occupancy detection, or heart-rate monitoring, where performance and energy efficiency are both important. The first part of this thesis describes a custom IC for gesture recognition radar demonstrating state-of-the-art energy efficiency. The IC consists of four transmitters and four receivers with shared frequency generation circuitry, and is packaged onto a 1.2x1.2cm antenna module containing eight antennas.

The other key application for mm-Wave technology has been for wireless communication. Products are finally coming to the market now that offer nearly 5 Gigabits per second of wireless data throughput for indoor wireless LAN applications, and mm-Wave technology will likely play a role in the next generation of wireless cellular standards as well. To demonstrate the possibility for yet-higher data rates to be achieved, a broad-bandwidth custom integrated circuit transceiver has been designed targeting a factor of 10 improvement in wireless data throughput beyond commercially available technology. The second half of this thesis will discuss the details of a transceiver and antenna design for broad-bandwidth and high data rate operation.

Research in the mm-wave band using CMOS and SiGe technologies has gained momentum over the past few years. Millimeter-wave circuits are expected to enter consumer electronics in the near future. 60GHz circuits have the potential to be used in high definition wireless video transmission and high data-rate point-to-point communication. 77GHz has been explored for automotive radar and is expected to become more ubiquitous in coming years. 90GHz has been investigated for imaging and remote sensing applications.

Raw silicon transistor performance has improved dramatically in the past decade, which has spurred much of the research. The potential low cost of silicon ICs, especially CMOS, is great motivation to design mm-wave circuits for volume production.

This dissertation is divided into two parts. In the first part, the design of a

60GHz CMOS receiver is presented. Design methodologies for robust operation at 60GHz are introduced at device and circuit levels. Key building blocks of a 60GHz receiver are investigated and several design techniques are proposed to increase the performance of the 60GHz circuits. Second part explores the potential of mm-wave design for imaging applications. Performance requirements and challenges of a 90GHz power amplifier for imaging applications are explored. Circuit and system level design details of a pulsed power amplifier are provided and methodologies for enhancing the performance of those designs are introduced. In the end, A prototype of this power amplifier and its integrated version in an ultra wideband pulsed transmitter are presented.

This thesis is expected to provide a design framework for achieving predictable and desired performance at mm-wave band.

With the proliferation of wireless standards and frequency bands, the manufacturers of consumer electronics have tried to integrate many features in a single hand-held device. This has given rise to a need for receivers that are compatible with as many standards and frequency bands as possible. Most current integrated multi-band receivers rely on multiple receiver front-ends to process signals at different bands. The major drawback of this approach is that each front-end must be individually optimized, resulting in longer design-time and higher silicon die areas. This is due to the number of circuit blocks and interface complexity. In addition, this type of implementation is highly standard-specific: thus, it is likely that a major redesign would be required if the same topology were used for different standards.

The primary objective of this research is to investigate efficient ways of implementing such a receiver front-end with minimal cost, power consumption, and design complexity. CMOS will be the targeted process technology for this design, due to the opportunities for analog-digital system integration and cost-reduction. Despite its attractiveness, designing a front-end for multi-band operations in deep-submicron CMOS technology is non-trivial. The main challenge lies in maintaining moderate gain, noise figure, and linearity at minimum current consumption across a wide frequency spectrum with the abating supply voltage.

In this work, we investigate and discuss several receiver front-end building blocks and system designs, with a focus on the issues that arise when designing a multi-band receiver front-end. In addition, we propose several circuit building blocks and systems, and implement design prototypes to validate the possibilities. The results suggest that by exploiting high-speed CMOS transistors and innovative low-voltage design techniques, it is possible to design a low-voltage, low-power, wideband receiver front-end path that is capable of processing signals using the proposed architectures.

Technology developments have made CMOS a strong candidate in high-frequency applications because of its low power, low cost and higher-level integration. However, as an essential element in an RF building block, a CMOS device is not as good as a BJT device in terms of speed and a HEMT device in terms of noise performance. Therefore, conventional low-frequency design techniques for CMOS circuits may not satisfy the requirements for high-frequency applications wherein the operating frequencies get close to the cut-off frequency of a CMOS device. This research work explores design techniques for various high-frequency circuits at 10 GHz, 60 GHz and up to 110 GHz. Individual building blocks including low-noise amplifiers, voltage-controlled oscillators, high-frequency true-single-phase-clock frequency dividers, and mm-wave amplifiers are studied thoroughly using both theoretical analysis and practical circuit designs. Related fundamental techniques, such as MOS device modeling and de-embedding techniques, are also explored. Furthermore, as a prototype of system-level integration, a Ku-band LNB front-end is implemented for the application of a satellite receiver.

The last decade has witnessed a tremendous growth in wireless communications. Consumer demands for battery-operated mobile devices with versatile, high data-rate communication capabilities that are of low cost, small form-factor and long operating cycle have motivated the research on fully-integrated, back-off-efficient and coexistence-friendly wireless transceivers in CMOS VLSI technology. However, the full integration of an efficient CMOS power amplifier (PA) into such a transceiver is still among the most difficult challenges towards a true System-On-Chip (SOC) solution. This thesis investigates the PA efficiency enhancement techniques for a complete power transmitter system that is fully-integrated and coexistable. Direct digitally modulated transmitter architecture has been identified as one of the most promising solutions to the above challenges. Within such a transmitter, the PA efficiency is able to back off from a high peak efficiency at least with class-B characteristic; meanwhile, the transmit linearity can be more easily improved by digital predistortion due to the direct digital modulation scheme. To validate such a promising architecture, we have built a fully-integrated CMOS digital power transmitter for the IEEE 802.11g 54Mbps application. System-level considerations and design choices are presented with an aim for low out-of-band noise and good transmit linearity. As the core of the transmitter, the RF switching PA is designed for high efficiency with minimum number of on-chip passives that only exercise an accurate control over fundamental and second-harmonic terminations. The class-B efficiency back-off characteristic is further improved by a dynamic impedance modulator which boosts the PA drain impedance at a low instantaneous envelope level. Open-loop phase interpolator based topology is used for the polar phase modulator, which achieves wideband phase modulation with competitive power consumption. Digital baseband filtering is fully optimized at both the algorithm and the hardware level, which offers larger than 60dB attenuation on the close-in spectral images with reduced filter complexity. The prototype has been implemented in a 65nm bulk CMOS technology and has demonstrated a combination of good output power, overall efficiency and spectral purity with a very high level of system integration.

The last decade has witnessed a tremendous growth in wireless communications. Today's consumers demand wireless systems that are low-cost, power efficient, reliable and have a small form-factor. This quest for ubiquitous wireless connectivity and the trend toward highly integrated solutions have opened up a new wave of challenges and opportunities for RF (radio-frequency) integrated circuit design. Since it often dictates both battery life and form factor, the transmitter - and in particular the power amplifier (PA) - is often the most challenging block in this integrated radio design. The grand vision for wireless transmitters is to merge as many components as possible, if not all, into a single die in an inexpensive technology. There is therefore growing interest in utilizing CMOS technologies for power amplifiers (PAs). However, the low-supply voltage of nanoscale CMOS technology, the loss of on-chip passives and the conductive silicon substrate make a fully-integrated PA design challenging. This thesis focuses on the design of fully-integrated PAs for modern wireless communication systems at RF (2.4GHz) as well as 60GHz frequencies. Transformer based matching networks have been studied for PA design and new modeling methods proposed in this work. It has been shown that there is tremendous area benefit of using transformers at 60GHz, while still preserving high performance. A prototype of a transformer-coupled PA has been designed at 60GHz in 90nm CMOS technology. The transformer design and modeling proposed at 60GHz is equally valid at RF frequencies. However, the high output power and high linearity requirements at RF frequencies create further challenges. Conventional power amplifier architectures are showing limitations in terms of achievable efficiency and area reduction. In particular, such architectures are not benefiting much from technology scaling since the area is dominated by passive elements. In this thesis, we investigate a mixed-signal power amplifier architecture. By merging our work on transformer-coupled PAs with a digital signal processing framework, a truly scalable, efficient transmitter architecture can be created. Such a prototype has been designed and tested in 65nm CMOS technology.

Wireless technology is facing several important trends. Growing demand for throughput and capacity on one end, and the ever-increasing push towards ubiquitous connectivity on the other end, have strained current systems and standards. Energy efficiency remains a critical issue for all of these applications, and has become an important challenge to balance in face of higher performance requirements. New applications and standards require radio systems that can provide multi-Gb/s wireless links on mobile devices with minimal impact on battery life. On the other side, connectivity is projected to move from people to objects in the realm of Internet of Things (IoT), scaling to trillions of radios in the next decade. This work addresses capacity and connectivity demands for next-generation radios.

In the area of IoT, ultra-low power highly miniaturized smart radios that can provide unique IP addresses and their locations are an important requirement of the system. In this context, battery-less radios are the ultimate frontier in scaling the size and cost of a communication node. However, there are several key challenges that still need to be addressed in this area. Cost (dominated by antenna board and interface), number of readable transponders (and latency in doing so), data-rate capacity, localization and miniaturization are the issues faced by today's designers. To overcome these challenges, a new approach for miniaturization of smart passive radios is proposed. We demonstrate a single-chip 24GHz/60GHz radio implemented in 65nm CMOS. This millimeter-sized chip radio is fully self-sufficient with no pads or any external components (e.g. power supply).

In order to address capacity demands, the 60GHz band with 7GHz of unlicensed spectrum provides a unique opportunity. A shift to mm-wave systems also enables beamforming by phased-array systems, which is critical in interfacing with the proposed passive radio. How- ever, integration, energy efficiency, and system cost remain to be obstacles in this space. In the second part of this thesis, we propose new system and circuit solutions and strategies for this application, and demonstrate an example design with a 4-element 60GHz phased-array receiver in 65nm CMOS. Energy and area efficiency is achieved by utilizing a baseband phase shifting architecture, holistic impedance optimization, and lumped- element based design. Finally, to enable scalability to larger arrays and to support hybrid RF/IF phase shifting, a lumped-element architecture for 60GHz phase-shifters is proposed and is shown to achieve low loss in a compact form factor.

For several decades, rapid improvements in the semiconductor industry, particularly the scaling of CMOS processes, have enabled high-speed wireless communications. However, the scaling of CMOS processes seems to be paying off less and less. Moreover, as the carrier frequency increases, the limited power of the CMOS chip can be quickly dissipated by passive elements or at the edges of the chip. The next generations of high-speed radios will require co-design and co-optimization of the chip and package to ensure that the highest data rates are achieved.This work addresses the design of a packaged wideband millimeter-wave radio. The fun- damental limitations of the CMOS process for millimeter-wave applications are examined. Noise measure theory is used to design low-noise amplifiers near the device activity limits. New techniques for minimizing the insertion loss of passive matching networks are proposed. The challenges of a package design are investigated, and an optimized transition structure is proposed. Finally, a 140GHz wideband receiver operating at half the transit frequency of the technology is implemented.

Clock generation circuits are essential building blocks that need to provide precision timing and frequency references for the whole system. Spur and phase noise are two of the most critical impairments of clock spectral purity that ultimately limit the performance of a communication system such as spectral emission, error-vector-magnitude (EVM) for transmitters and the blocker tolerance for receivers. Therefore, it would be worthwhile to develop a post-processing module cascaded after the clock source and perform the spectral purification to recover and even boost the performance.

Two techniques for spur and phase noise cancellation have been proposed. With analog- signal-processing by delay lines we can synthesis the desired shape of the transfer function for spectral filtering, such as notches to reject far-out spurs, and high-pass filtering to suppress close-in phase noise. A fully integrated design achieves a measured spur cancellation of 15dB at 250MHz and 750MHz offset as well as phase noise cancellation from 4MHz to 200MHz offset with maximum 25-dB cancellation depth for a 1-GHz clock. The proposed ideas have been verified through a fabricated 65-nm CMOS prototype with power consumption of 11mW from a supply voltage of 1.2V.

Furthermore, we will demonstrate a novel clock multiplier architecture that achieves low jitter and also insensitive to frequency drift without a continuous frequency tracking loop (FTL). With the proposed digital spur calibration techniques, the spurs can be effec- tively suppressed down to −50.9dBc. Fabricated in 28-nm CMOS technology, this prototype presents an integrated jitter of 138fsrms while consuming only 6.5mW from a 1-V/0.8-V supplies and achieving −249dB FoM. A detailed study on the mechanisms of jitter perfor- mance affected by frequency drift is included, which provides a theoretical justification to the approach. Also, the time domain/frequency domain analysis on digital spur calibra- tion are discussed as well. Finally, an improved version with lower power consumption and generalized multiplication ratio is also realized in a test chip in 28-nm CMOS technology.

The explosion in demand for wireless capacity has been a strong driver for cellular network modification. Previous solutions to this problem have involved an increase in available channel spectrum to each user and an increase in bands used for cellular communication. This practice has led to an extremely crowded low-frequency spectrum, where the significant problems now are not processing high bandwidths in a mobile device, but instead managing the interference caused by high-traffic scenarios.

One of the most challenging instantiations of this interference mitigation problem is Frequency Division Duplex (FDD) communication in the Long Term Evolution (LTE) standard, where a cellular device both transmits and receives information simultaneously, but in separate frequency bands. Globally, there are 40 LTE FDD bands, and in the worst cases, the center-to-center spacing of transmit (TX) and receive (RX) bands is only twice the bandwidth. With 120dB of dynamic range between the TX and RX signals, without significant isolation, the RX is heavily desensitized or even damaged by the high power TX signal. This problem is currently solved with fixed external duplexers, which provide high TX/RX isolation, but at the cost of frequency tunability. Due to the large number of TX/RX frequency band pairings present in the LTE standard globally, using fixed filters for isolation is infeasible if a phone is to operate well internationally.

In this thesis, a fully-integrated, highly frequency-flexible method for TX self-interference cancellation is proposed, where a mixed-signal canceller is employed at the input of the RX. This technique is shown to allow the receiver to tolerate high TX power levels over a large variety of channel and transceiver nonidealities. The deterministic TX-band interference signal is shown to be mitigated within this system, along with the non-deterministic sources of interference from TX phase noise and canceller thermal noise. Finally, further reduction in TX interference in the digital backend using digital modelling of the PA, canceller, and duplex network is shown.