As the number of wireless network users increases in the modern communication systems, cognitive radio becomes an attractive solution to the crowded communication spectrum. A key technology that enables the application of cognitive radio is the circuit that can sense the available spectrum for communication, as known as: Spectrum Scanner. Previous work has demonstrated a passive spectrum scanner using the sampled LPTV RC circuit that achieves 0-1Ghz scanning range and 40dB stopband attenuation. However, the parasitic capacitors in the resistor DAC limits the stop band attenuation from 60dB to 40dB. Chapter 1 and 2 will provide the background of sampled LPTV RC filter as a spectrum scanner. Chapter 3 will provide the analysis of parasitic capacitor's effect on filter's frequency response and a RDAC switching technique as a solution. Chapter 4 and 5 present the circuit design of a 0-3Ghz spectrum scanner using return-to-infinity RDAC to remove parasitic capacitor's influence on filter's stopband attenuation.

Due to the proliferation of frequency bands that need to be supported in wireless standards, such as LTE, GSM, 5G, etc., modern wireless transceiver designs rely on numerous off-chip SAW/BAW filters and many on-chip LC tanks, which are typically not very tunable. On the receiver end, this is because wireless signals typically possess vastly different strengths, and such large signal strength differences necessitate the receiver front-ends to be low-noise and linear, while providing sharp filtering. Hence, conventional approaches resort to passive off- and on-chip band-pass filters. Not only are these filters bulky, but they generally have fixed bandwidths and center frequencies, therefore a number of them are needed, occupying a lot of PCB and chip area to cover multiple bands. Consequently, it has been of significant interest in recent years to explore high-programmability SAW/BAW-less transceivers for emerging software-defined and cognitive radio applications. However, without the pre-filtering provided by SAW/BAW filters, such receivers face great challenges in providing sufficient performance in the aforementioned aspects simultaneously. Some recent approaches include N-path filters (NPFs), mixer-first receivers, and discrete-time (DT) charge-domain signal processing. They have demonstrated some level of programmability, while providing reasonably good performance, yet their overall performance has not reached that of their counterparts using off-chip SAW/BAW filters and/or on-chip LC filters.

In this work, we explore the newly developed filtering-by-aliasing (FA) technique to build receiver front-ends using periodically time-varying (PTV) circuits. The FA technique essentially realizes sharp baseband analog FIR filtering. In conjunction with a mixer, the FA receivers offer one of the sharpest band-pass filters achieved with CMOS technologies to date and extremely high programmability. However, they also face a few problems, including relatively high noise, moderate linearity, sensitivity to parasitics at RF, and residual aliases that cannot be further filtered. They limit the ultimate dynamic range that FA receivers can achieve, and prevent wider adoption of FA receivers. This research looks into enabling techniques to enhance the dynamic range of FA receiver front-ends in order to make them more practical. A technique based on PTV noise cancellation was proposed to effectively lower the noise figure (NF) of the receiver, while maintaining the FA sharp filtering. Measurement results show an improvement of about 3 dB on NF, while simultaneously achieving 67-dB stopband rejection with a transition bandwidth of 4� the RF bandwidth. In conjunction with an up-front NPF, an out-of-band IIP3 of +18 dBm and a blocker 1-dB compression point of +9 dBm have been demonstrated. Moreover, an innovative slice-based FA architecture with all switches moved inside the feedback network has been proposed for FA receivers in this work to provide support for carrier aggregation and improve linearity. The fabricated prototype in 28-nm CMOS demonstrated two-channel concurrent reception with filters that achieve 50-dB stopband rejection with a transition bandwidth of 3.2� the RF bandwidth. It has also shown +35-dBm IIP3 and +12-dBm blocker 1-dB compression point with a supply voltage of only 0.9 V, whereas a low LO leakage of -81 dBm was also demonstrated. Further, a residual alias cancellation technique for FA receivers has been proposed and demonstrated on a dual-channel FA receiver. With measured frequency responses of the receiver, digital baseband filters are designed to cancel the residual aliases. Built in MATLAB, the proposed alias cancellation algorithm achieves about 15-dB alias suppression on measured data in addition to the analog FA filtering.

Wide programmability is increasingly desirable in transceiver designs. Due to the proliferation of frequency bands that need to be supported in wireless standards, such as LTE, WiFi, etc., the continued reliance on bulky off-chip SAW/BAW filters and on-chip inductors in current receiver designs is increasingly untenable. Hence, more integrated approaches are necessary, especially for future radio concepts, such as cognitive radios (CRs), where the channel bandwidth and center frequency are dynamic and not known a-priori. Current state-of-the-art on-chip receiver designs rely on techniques such as discrete-time analog signal processing, N-path filtering, and the mixer-first receiver topology. Nevertheless, on-chip filtering still does not approach the selectivity or linearity of their off-chip counterparts. Hence, new approaches are necessary.

This work presents a programmable receiver front-end that uses the recently developed concept of Filtering-by-Aliasing (FA). By utilizing a linear, periodically time-varying (LPTV) circuit with a sampled output, sharp baseband filtering is achieved that can be upconverted to any desired LO frequency with an integrated passive mixer. Further, to achieve impedance matching with the antenna, an S11 constraint is added to the design of the FA filters, while time-interleaving is applied to further increase filter sharpness. Measurements on a fabricated prototype achieved a wide LO tuning-range of 0.1-1GHz, wide filter bandwidth (BW) tunability, a filter stop-band suppression of 70dB with a transition band only 4xBW, high close-in blocker tolerance with >21dBm IIP3 at only 1.2xBW offset frequency, and a wideband S11 better than -9dB throughout the LO range. Further, an analysis technique for general LPTV circuits is developed utilizing the concept of conversion matrices. By deriving conversion matrix-based frequency-domain equivalent circuits, LPTV circuits can be analyzed just like LTI circuits. Circuit laws, such as KVL and KCL can be easily applied to derive frequency responses. Example applications to mixer-first receivers, N-path filters, and the problem of impedance matching in LPTV circuits are highlighted to showcase the utility of the analysis technique.

Spectrum sensing finds its use is many applications. With modern communication systems moving towards Cognitive Radios (CRs) to better utilize the available spectrum, spectrum sensing is a key enabling functionality that allows the detection of primary users and interferes to support spectrum sharing. Spectrum sensing can also be useful in security applications that require a certain degree of RF spectrum awareness. In addition, it can be used for built-in self-test like transmitter tuning by measuring the output spectrum to allow spur reduction and digital predistortion.

To be useful, the spectrum scanners used for sensing should be able to handle large blockers and detect weak signals at the same time. Thus both good linearity and high sensitivity are desired. In addition, these scanners need to be highly programmable and selective while incurring a low power cost.

In this research we have addressed the issues that plague traditional spectrum scanners by using the recent technique of Filtering by Aliasing (FA). The FA-based spectrum scanner is a passive structure that uses simple but linear, periodically time-varying (LPTV) RC circuits. This LPTV circuit is shown to provide a high spurious-free dynamic range, precise resolution bandwidths while still consuming very low power.

In this dissertation, the FA technique is briefly explained, and the design considerations and implementation of a spectrum scanner IC that achieves excellent linearity and low power as compared to state-of-the-art designs is presented. In addition, a theoretical analysis of some of the limiting factors of the passive LPTV scanner is presented together with some circuit and/or signal-processing solutions.

Chapters 2 and 3 of this dissertation are the reprint of a paper that is to be published in full in the IEEE Journal of Solid-States Circuits (JSSC). The dissertation author is the primary investigator and Professor Sudhakar Pamarti supervised the research which forms the basis for this paper. Dr. Mansour Rachid and Professor Shanthi Pavan from IIT, Madras collaborated on this work as well.

Chapters 4 and 5 of this dissertation are the reprint of a paper under preparation to be submitted in part or in full to the IEEE Transactions of Circuits and Systems-1 (TCAS-1). The dissertation author is the primary investigator and Professor Sudhakar Pamarti supervised the research which forms the basis for this paper. By the virtue of being independent papers, there is a slight degree of content overlap between Chapters 2-3 and 4-5.

Contemporary high-spectral-efficiency communication systems increasingly rely on complex modulation, with high-order constellations and multi-carrier signaling. These formats often have high peak-to-average-power ratios (PAPR). It is difficult to design power amplifiers (PAs) for high PAPR signal with good power efficiency and linearity simultaneously.

Strategies to improve power efficiency fit into established amplifier classes. Some aim to reduce standing current; others reduce supply-voltage overhead. There are also switch-mode classes and load-modulation classes. PA design arts using these classes alone or in combinations achieve good power efficiency for narrowband high-PAPR signals. However, these existing arts lack effective techniques for wideband systems. One of the bottlenecks is the limited-speed supply modulation.

There are several linearization schemes that have been presented to mitigate PA’s nonlinearity. Among these, digital pre-distortion (DPD) is currently the most popular. However, the conventional architecture, ADC-based DPD, requires high speed/resolution ADC, which is high cost and power hungry. It also requires large processor power and memory for time-domain information.

Two techniques are proposed to address the challenges of broadband Class-AB PA’s power efficiency and linearity separately. For efficiency enhancement, we introduce Instantaneous Supply-Switching technique. This technique improves efficiency by high speed current-mode supply-switching in response to instantaneous signal, unlike most prior supply modulation implementations which only responds to the signal envelope. For linearity improvement, we introduce Signal-to-Distortion-Ratio(SDR)-based DPD technique. This methodology only requires the power information of signal- and distortion- channel, which is more data efficient than ADC-based DPD. The hardware for SDR-based DPD therefore potentially has lower cost and power.

The intended application in this dissertation is cable TV upstream power amplifiers.

Aggressively duty-cycling the operation of a system between ON and OFF states has proven to be the most effective way to reduce the average power consumption in energy-constrained applications such as Internet-of-Things (IoT). Since these devices are either battery-powered with a very small form factor or rely on energy harvesting where small amount of ambient energy is captured to power up the device, ultra-low power consumption is crucial in enabling all the advantages that applications such as IoT and biomedical implantable/wearable devices are expected to produce. However, the amount of power saving in a duty-cycled system is usually constrained by two main factors: 1) the start-up time of the system; and 2) the OFF-state power consumption. The system start-up time is usually limited by the long start-up time of its reference oscillator, typically a high-Q, MHz-range crystal oscillator that usually takes several milliseconds to turn on. The OFF-state (sleep) power consumption, on the other hand, is dominated by the sleep timer that is an always-ON 32KHz crystal oscillator. Sleep timer synchronizes the transmitting and receiving bursts which requires a very accurate oscillation frequency to minimize the guard band in order to reduce the active energy consumption. To address the mentioned challenges, we have developed circuit techniques and architectures that enable low-power clock generation.

To kick-start high-Q oscillators, such as crystal and/or MEMS-based reference oscillators, pre-energization of the resonator through injecting energy for a precise duration is proposed. A universal analysis for energy injection into high-Q resonators is developed and used to calculate the optimal injection duration essential to obtain a minimum start-up time. The proposed method ameliorates the sensitivity of the start-up time to the matching between the injection and resonance frequencies. To further relax the frequency accuracy requirement of the injection oscillator, energy injection with a dynamically-adjusted injection duration is presented. Measurement results from a 65nm CMOS IC show that the proposed technique reduces the start-up time of multiple tested crystal oscillators to about 100-120 number of oscillation cycles. The measured start-up time using the proposed precisely-timed energy injection method is 15 times faster than the best case reported in the literature while consuming the lowest start-up energy of ~12nJ.

In order to reduce the sleep power consumption, an ultra-low power sleep timer that is based on a DC-only sustaining amplifier is presented. New oscillator architecture is proposed that enables sub-nW power consumption in a 32KHz crystal oscillator by amplifying the oscillation signal at DC, instead of amplifying it at the oscillation frequency. Measurement results of 20 different 65nm standard CMOS dies show an average power consumption of 0.55nW drawn from a 0.5V supply at room temperature for a 32KHz crystal oscillator. The measured long-term stability of the sleep timer indicated by the Allan deviation floor is 14ppb. The proposed oscillator architecture does not require any calibration schemes or multiple supply domains, unlike most prior art.

The rapid rise in demand for high data rates has led to communication standards like LTE that use signals with wide signal bandwidth and high peak-to-average power ratio. Since, total power consumption is largely determined by the efficiency of the power amplifier used, high efficiency architectures like polar and out-phasing, are preferable for future transmitter designs. Such architectures require a phase modulator (PM) as one of their key building blocks. The recent developments in phase modulator design have demonstrated superior wide-bandwidth performance of open loop modulation techniques. However, currently the resolution is limited by systematic errors inherent in the phase modulator circuit and random errors due to inevitable component mismatches.

In this dissertation, a phase-interpolator based open-loop phase modulator is proposed, which leverages a digital calibration technique to mitigate the sources of phase errors and achieves excellent phase resolution. At the heart of this technique, a time-to-digital converter performs high resolution measurement of phase errors of the phase modulator. These measurements are used to continuously pre-distort the modulation data, so that the linearity of the overall transfer function is enhanced, thereby resulting in low out-of-band emission and low in-band noise. A prototype IC was implemented in 0.13 m CMOS process. Measurements on the prototype show that out-of-band quantization noise is 56-dB lower than the signal when transmitting 20-Mb/s GFSK signal and the r.m.s. error is only 3.2%. The power consumption of the phase modulator is 18 mW. Since the IC was implemented in 0.13 m CMOS process, the power is expected to reduce a lot, if it is implemented in finer process nodes. The dissertation also presents theory and measurement results on frequency synthesis using the open-loop phase modulator. New frequency can be synthesized with very fine frequency step size, by applying a digital phase ramp to the phase modulator. However, the non-linearity of the phase modulator results in strong spurious tones. Digital compensation is proposed to mitigate these spurs, and generate multiple low-jitter clocks.

Many portables and IoT devices employ multi-radio systems. The number of differenttransceivers/antennas is increasing, especially with multi-antenna and phased array systems. Operating multiple transmitters, power amplifiers, and antennae in close physical proximity, simultaneously, in nearby frequency banks leads to unwanted TX-to-TX signal coupling which, in the presence of power amplifier non-linearity, causes intermodulation distortion products (IMD3) that are problematic e.g., causing transmit spectral mask violations. There is a strong need to eliminate or suppress such TX-to-TX signal coupling and the IMD3 products to satisfy FCC spectral mask requirements and enable simultaneous multi-band transmission. Prior work has explored TX-TX cancellation for simultaneous transmission of NB and WLAN signals using analog techniques. However, the analog implementation is bulky and power hungry. A digital implementation for TX-TX self-interference cancellation can alleviate these issues. This thesis explores the design and implementation of a Digital-to-Time-Converter(DTC) as a part of digital TX-TX cancellation for the simultaneous transmission of NB and WLAN signals in 22FDX Technology. The designed DTC demonstrates consistent performance across process and temperature corners without calibration and has the necessary step-size and range to meet the TX-TX cancellation requirement.

Deep learning is creating many new applications on edge devices such as autonomous driving, industrial robotics, and wearable health care. Edge devices demand hardware operating at low power, but processing with a high throughput. Traditional digital Von Neumann architecture such as CPU and GPU is limited by the data movement's cost. The computing challenge demands more efficient memory technology and architectures. Voltage-Controlled Magnetic Tunneling Junction (VC-MTJ) is an emerging MRAM solution that can achieve much higher density than SRAM and more efficient write operation than other MRAM technologies. VC-MTJs not only can be used as memory devices but also in cryptography and probabilistic computing applications such as Stochastic Computing (SC). VC-MTJ's special voltage-controlled switching behavior can achieve stable, but random, switching probability after a long pulse and removes the requirement of calibration circuit. We have demonstrated a VC-MTJ based TRNG in 65nm, which passed the NIST randomness tests. Compute-In-Memory (CIM) is an emerging solution to move computing inside the memory to avoid data access. Entire array can be activated for computing and, therefore, breaks the bandwidth limits of Von Neumann architecture. Stochastic Computing (SC) is an approximate computing method that uses extreme tiny bit-serial logic gates as computing unit to achieve massive parallelism on chip. Combining SC and CIM removes the costly Analog-to-Digital converter (ADC) of traditional CIM architecture and achieves high energy efficiency. The compact SC computation units can also achieve massive throughput density inside memory. In the second half of this thesis, we propose combining the benefits of SC and CIM as Stochastic Compute-In-Memory (SCIM) accelerators. We have demonstrated two variants of the SCIM solutions: (1) An SCIM accelerator in 65nm supporting full CNN operations on chip with 8-bit precision for image classification applications. The memory stores pre-converted stochastic bit stream and achieves high energy efficiency by in-memory SC MAC units. (2) An SCIM accelerator in 12nm for high-speed object tracking application using event cameras. The memory embeds in-situ stochastic number generator to allow binary number storage and achieves >30x higher throughput density than state-of-the-art works.

Dynamic element matching (DEM) has been widely researched in the domain of digital-to-analog converters. Different architectures, noise shapes and ever higher order shaping have been devised. However, beyond first order, no schemes guarantee the absence of tones. Herein presents a band-pass shaping scheme that is provably toneless based on tree structured DEM. This scheme does incur a noise penalty and additional hardware. However, the former of which can be controlled and the later of which is only moderate.