Behaviors describing image processing algorithms manipulate arrayed variables that are typically mapped to memories. These algorithms form the heart of portable communication and multimedia applications that demand low power, hence power reduction of memory systems is a critical task.
In this report we present low power techniques for mapping arrays in the behavior to physical memory, specifically for memory intensive behaviors that exhibit regularity in their memory access patterns. Our approach exploits this regularity in memory accesses by reducing the number of transitions on the memory address bus.
We present different strategies for mapping arrays in behaviors to physical memory and study their impact on power dissipation. We describe an algorithm for selecting a memory mapping strategy to achieve low power. We conducted experiments on several image processing benchmarks and observed power savings of upto 56 % through reduced transition activity on the memory address bus.