This dissertation consists of two parts. In the first part, a broadband universal receiver is proposed with channel selection and blocker rejection that achieves a low noise figure and high linearity through an innovative use of feedback techniques. It also demonstrates ample harmonic rejection owing to its newly proposed harmonic trap method with no calibration required. Realized in 28-nm CMOS technology, the receiver exhibits a noise figure of 2.1 dB and a third and fifth harmonic rejection of more than 60.8 dB up to 2 GHz while consuming 49 mW.

In the second part, we introduce a a new linear, time-variant model that provides a general framework for understanding and modeling of injection locking in oscillators and frequency dividers. Application of the proposed model to direct injection locked frequency dividers (DILFDs) results in new insights and design optimization criteria which highly improves the divider lock range and power consumption. Two DILFD prototypes have been fabricated: A 1.88-mW single DILFD that operates from 26 GHz to 63 GHz and a 4.76-mW coupled DILFD that operates from 24 GHz to 73 GHz with no need for tuning or adjustments.

A 300-GHz heterodyne receiver downconverts the input to an IF of 27 GHz and performs quadrature separation, thereby avoiding the need for power-hungry couplers and phase splitters. The LO generation consists of a 270-GHz fundamental-mode subsampling PLL with offset mixing driven by a 108-GHz PLL and a 54-GHz PLL. Fabricated in 28-nm CMOS technology, the receiver provides a voltage gain of 18 dB with a noise figure of 20 dB with I/Q gain mismatch of 1.2 dB and phase mismatch of 5.4 degrees.

Recent developments in RF receiver design have eliminated all on-chip inductors except for that used in the local oscillator. This dissertation addresses the “last inductor” problem and proposes both integer-N and fractional-N synthesizer architectures that achieve a phase noise and figure of merit (FOM) comparable to those of LC-VCO-based realizations.

A new wideband integer-N synthesizer is introduced to sufficiently suppress the ring’s phase noise. It employs an exclusive-OR (XOR) phase detector and a master-slave sampling filter (MSSF) to achieve a lock range of 2-3 GHz, a loop bandwidth equal to one half of the reference frequency, and a locked phase noise of -114 dBc/Hz up to 10-MHz offset with a 3-stage ring oscillator. Realized in 45-nm CMOS technology, the design uses a harmonic trap to suppress reference sidebands to less than -65 dBc while consuming 4 mW.

The wideband architecture has been successfully extended to a fractional-N loop as well. A ring-oscillator-based cascaded synthesizer incorporates a digital synchronous delay line and an analog noise trap to suppress the quantization noise of the Sigma-Delta modulator. Realized in 45-nm CMOS technology, the synthesizer exhibits an in-band phase noise of -109 dBc/Hz and an integrated rms jitter of 1.68 ps at 2.4 GHz with a power consumption of 6.4 mW.

The problem of clock generation with low jitter becomes much more challenging as wireline transceivers are designed for higher data rates, e.g., 224 Gb/s. This dissertation addresses the clock generation problem and proposes both integer-N and fractional-N phase-locked loop architectures that achieve low jitter with low power consumption. This dissertation consists of two parts. We first introduce an integer-N PLL that incorporates two new techniques. A double-sampling architecture samples both the rising and falling edge of the reference clock, which improves the in-band phase noise by 3 dB. Also, a robust retiming technique is presented to reduce the phase noise of the frequency divider. Fabricated in 28 nm CMOS technology, the 19-GHz prototype achieves an rms jitter of 20.3 fs from 10 kHz to 100 MHz with a spur of -66 dBc, all at a power of 12 mW. Next, we propose a 56-GHz fractional-N PLL targeting 224-Gb/s PAM4 transmitters. The PLL employs a novel current-mode FIR filter to avoid phase and frequency detectors (PFDs) and charge pumps and to suppress the DSM quantization noise with negligible noise folding. To provide a compact solution suited to multi-lane systems, the PLL also incorporates an inductorless divide-by-8 circuit that draws 3.1 mW. Fabricated in 28-nm CMOS technology, the PLL exhibits an rms jitter of 110 fs, consumes 23 mW, and occupies an active area of 0.1 mm2.

The growing demand for high-speed communication has led to a twofold increase in the per-lane data rate every four years across various wireline standards. As a result, the power consumption of high data rate transceivers has become critical. Moreover, the bandwidth of different blocks within a transceiver must accommodate the operating speed so as to avoid eye closure. These concerns call for either implementation in expensive sub-10nm FinFET technologies, or new circuit- and system-level novelties realized in less-advanced CMOS nodes.This work introduces a PAM4 transmitter (TX) that incorporates a number of new techniques to achieve a low power consumption, while delivering data at 112 Gb/s. A resistorless voltage-mode output DAC relies merely on the on-resistance of the transistors within LSB and MSB inverters for proper termination, thereby relaxing the capacitive loading of the data and clock paths, hence lower power. The PAM4 nonlinearity due to nonlinear resistances is alleviated by scaling up the LSB section, as well as employing separate LDOs for LSB and MSB for fine calibration. Furthermore, a 3-tap latchless FFE provides a high-frequency boost with minimal power. Lastly, a new skew compensation network adjusts the skew experienced by the differential signal in an asymmetric channel. The TX includes a latchless serializer and an on-chip PLL. Fabricated in 28-nm CMOS technology, the transmitter draws 58 mW and exhibits a swing of 0.8 Vpp,d, rms clock jitter of 160 fs and RLM = 96%.

The design of RF integrated circuits continues to challenge engineers and researchers, demanding new circuit topologies and transceiver architectures. New ideas often require new analysis techniques as well, so that the designer can insightfully quantify the underlying principles.

This research addresses three problems in RF circuits: (1) analysis of phase noise in phase/frequency detectors (PFDs), an essential component in RF synthesizers; (2) analysis of the relation between the phase noise of delay lines and ring oscillators; and (3) design of a new low-power RF CMOS receiver for IEEE 802.11a. The first analysis derives equations for the phase noise and shows that

an octave increase in the input frequency raises the phase noise by 6 dB if flicker noise is dominant and by 3 dB if white noise is dominant. The second analysis reveals a simple shaping function and also dispels the commonly-accepted premise that symmetric rise and fall times in a ring oscillator suppress the upconversion of

flicker noise. The third part deals with the design of a low-power 5-GHz receiver. While advances in the art have considerably reduced the power consumption of RF oscillators, frequency dividers, and analog-to-digital converters, the main receiver chain in 5-GHz systems draws a disproportionately high power, about 46 mW. It is therefore desirable to develop low-power RX front ends and baseband filters for WiFi applications. This work introduces a complete 5-GHz CMOS receiver that meets the 11a sensitivity, blocking, and filtering requirements while consuming 11.6 mW. This fourfold reduction in power is achieved through the use of a transformer as a low-noise amplifier, passive mixers, and non-invasive baseband filtering. A new analysis of passive current-driven mixers sheds light on their properties.

Advancement in smart devices, development in cloud computing, and surge in Internet usage means an ever fast increase in demand for wireline communications, which include very-short-range chip-to-chip communications, data center interconnections, cross data center interconnections, and metro and long-haul communications. Four-level pulse-amplitude-modulation (PAM4) is proven to be the latest trend and replacement for traditional non-return-to-zero (NRZ) standards. Of current PAM4 standards, 56-Gb/s is one of the popular data rates to realize wireline data communication.

In PAM4 wireline communications, clock and data recovery (CDR) circuit is one of the most important building blocks, without which it is impossible to receive the correct input data and realize wireline data communication. In most applications, a typical CDR decides recovered clock jitter, loop bandwidth, and jitter tolerance. Regarding power consumption, for line-side applications, a CDR takes a significant amount of power (20% in some cases); while for host-side applications, a CDR uses most of the power. Therefore, we would like a CDR that has low recovered clock jitter, high jitter tolerance, low power consumption, and a proper loop bandwidth depending on specific standards.

A review of current works shows that, most recent PAM4 CDRs are still slicer based or ADC/DSP (Analog-to-Digital-Converter/Digital-Signal-Processing) based, which means an incoming PAM4 signal is transformed into NRZ signals first, and then they are processed with traditional NRZ approaches. Slicers or ADC/DSP usually lead to high power consumption, and/or heavy calibration.

This work proposes a new 56-Gb/s PAM4 CDR architecture. It uses a proposed phase detector (PD) design that processes PAM4 signal in analog domain by generating Euclidean distances among the samples. This work also proposes an analog background offset-cancellation scheme that makes the PD robust.

Realized in 28 nm CMOS technology, the CDR prototype consumes a total power of 8 mW. It has a 547-fs recovered root mean square clock jitter for a 160-MHz loop bandwidth and at least 1 unit interval (UI) jitter tolerance (BER < 10^-12) at 10MHz.

With the ever-increasing need for high throughput from chip-to-chip I/Os, wireline transceivers are being pushed to operate at higher speeds. With the increase in data rates, the power consumption of broadband receivers has become critical in multi-lane applications like the Gigabit Ethernet. It is therefore desirable to minimize the power drawn by all of the building blocks.

This work introduces a 40-Gb/s CMOS wireline receiver that advances the art by achieving a tenfold reduction in power and an efficiency of 0.35 mW/Gb/s. An innovative aspect of the proposed NRZ receiver is our “minimalist” approach, which recognizes that every additional stage in the data or clock path consumes more power and limits the bandwidth. The minimalist mentality avoids multiple stages in the front-end continuous-time linear equalizer (CTLE), quadrature oscillators in the clock and data recovery (CDR) circuit, clock or data buffers, or phase interpolation. Moreover, building blocks are shared among different functions so as to reduce the number of current paths between VDD and ground. Using charge-steering techniques extensively, the receiver contains only a few static bias currents adding up to about 6 mA. The minimalist approach also leads to a small footprint, about 110 um x 175 um, for the entire receiver, making it possible to design a multi-lane system in a small area and with short interconnects.

This receiver incorporates a one-stage CTLE with 5.5-dB boost, a one-tap discrete-time linear equalizer (DTLE) with 5.4-dB boost, a half-rate CDR circuit, a two-tap half-rate/quarter-rate decision-feedback equalizer, a 1:4 deserializer, and two new latch topologies. Since in recent designs, the CTLE draws significant power, this work introduces the DTLE as an efficient means of creating a high-frequency boost with only 0.3 mW. Fabricated in 45-nm CMOS technology, the receiver achieves a BER < 10^(-12) with a recovered clock jitter of 0.515 ps,rms, a jitter tolerance of 0.45 UI at 5 MHz, with a channel loss of 18.6 dB at Nyquist, while consuming 14 mW from a 1-V supply.

High-speed analog-to-digital converters (ADCs) are at the heart of many applications such as digital communication, video, and instrumentation. However, the power efficiency of ADCs tends to degrade as higher speeds and/or resolutions are sought. In this research, we introduce a low-power high-speed pipelined ADC

architecture that employs a precharged resistor-ladder digital-to-analog converter (RDAC) and a multi-bit front end with a low-gain op amp. Avoiding the need for op amp nonlinearity calibration, the ADC only computes the gain errors and corrects them in the digital domain. In addition, RDAC simplifies the calibration

logic and enables high-speed gain error calibration, thus correcting for the incomplete settling of the MDACs. Using simple differential pairs with gains of about 5 as op amps and realized in 65-nm CMOS technology, the 10-bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibits an FOM of 70 fJ/conv.-step.

A critical issue in the design of high-speed ADCs relates to errors that result from comparator metastability. Studied for only flash architectures, this phenomenon assumes new dimensions in pipelined converters, creating far more complex error mechanisms. In this dissertation, we present a comprehensive anal-

ysis of comparator metastability effects in pipelined ADCs and develop a method to precisely predict the error behavior for a given input signal p.d.f.