Because of their wide RF bandwidth (~1 THz) and high breakdown voltages (BV_CEO >3 V), npn-In_0.53Ga_0.47As/InP double heterojunction bipolar transistors (DHBTs) have extensive applications in monolithic microwave integrated circuits (MMICs) such as high performance transceivers, near-terabit optical fiber link, and THz amplifiers in radar/imaging systems. The improvements in the performance of DHBTs were made possible because of device scaling. As the technology advances towards the next scaling generations, new challenges in the manufacturing techniques and the device designs are met. The purpose of this work is to provide solutions to the problems encountered in the fabrication and design of the base-emitter junction while scaling from 200 to sub-100 nm emitter width.

Two important issues regarding the base-emitter junction arises while scaling towards sub-100 nm emitter width. The process flow for the refractory emitter metal stack developed for 250-100 nm emitter width has already reached its limitation. In order to improve the transistor yield at a reduced linewidth without designing a new process flow, revisions have been made to the existing one. Employing the revised process flow, 75 nm-wide emitter is feasible. The overall transistor yield has also been improved. This increases the number of working devices per sample, enabling thorough device analyses.

Experimentally, a reduction of current gain (β) associated with device scaling has been observed. In order to assess the causes of the reduction, the electron transport in the base is emulated by a commercial simulator. A model for DC-β at high injection current density (25 \mA/μm²) was constructed by the comparison between the experimental and the simulation results. The model allows the estimation of β which benefits the design of the future scaling generations of DHBTs.

It has been deduced from the model that the current originated from Auger recombination and lateral electron diffusion (via the surface and the bulk base semiconductor) are the dominant components that limit DC-β. To suppress the diffusion current via surface, a process flow is developed to form passivating sidewall onto the base surface. Such process flow has already been incorporated into DHBT fabrication. Moreover, new geometries for the base-emitter junction have been designed on the purpose of reducing the Auger recombination rate and lateral electron diffusion in the bulk base region. According to the simulation results, the new designs could potentially improve DC-β beyond 50 if the corresponding process flow could be adequately integrated.

This work presents the efforts pursued to improve InGaAs/InP FET technologies for high frequency applications. Self-Aligned MOS-HEMTs were developed using a sacrificial InP layer and a diluted HCl sacrificial etch. The new process removes the previous issue of misalignment in MOS-HEMT technology. In addition, the self-aligned process results in a new “V-gate” as opposed to the tradition “T-gate”. This new gate technology no longer requires the bi-layer resist used in traditional HEMT technology and allowed for gate footprint scaling from 50 nm to 20 nm. To improve processability and high frequency performance, a theory on the effects of topside link thickness on resistance, capacitance, and cut off frequency was proposed. Traditionally, HEMTs have thick link regions to keep the donor ions far from the mobile charge in the channel. This keeps scattering and resistance in the source low; however, this places more material in between the source and the gate and increases capacitance. Simply, the theory states that as transistors continue to scale, the mobility of the link becomes less dominant than the extrinsic source gate capacitance when considering optimal link thickness. In the new process, CGS + CGD was reduced by a total of 40% compared to previous MOS-HEMTs. With these improvements, a Lg = 20 nm device, exhibiting fτ = 525 GHz, fmax = 709 GHz, and a Lg = 36 nm device, exhibiting fτ = 479 GHz, fmax > 1 THz were demonstrated.

Future trends in wireless communication systems show rapid growth in mobile data traffic. The number of subscribed users per mobile base station grows linearly with time. Emerging immersive media formats and applications (i.e., HD/UHD, 360 videos, AR/VR) requires a higher data rate and larger channel bandwidth. Millimeter-Wave massive multiuser multiple-input multiple-output (MU-MIMO) is a potential candidate for high-capacity, high data rate wireless base stations. The available mm-wave spectrum between 100GHz to 300GHz is large. The small carrier wavelength (λ) permits compact arrays with many antennas; hence spatial multiplexing can be utilized to increase the system capacity.

This thesis explores system architectures, transceiver circuit design, and high-performance packaging technologies suitable for mm-wave and sub-THz multiuser massive MIMO arrays. First, we present a comprehensive study between potential mm-wave MU-MIMO architectures (all-digital, hybrid, and fully-RF) in terms of system dynamic range requirement. We draw guidelines on the required system front-end 1-dB compression point and the required analog-to-digital converter resolution for each architecture. We also illustrate the impact of system power control and antenna load factor on relaxing the dynamic range requirements.

Next, we present the core elements for our massive MIMO arrays. We designed and tested a single-channel direct conversion transmitter (Tx) and a single-channel direct conversion receiver (RX) using Global-Foundries 22FD-SOI technology, with a record measured 3-dB modulation bandwidth of 20GHz. The Rx has 27dB conversion gainand -30dBm P-1dB. The Tx has a saturated output power (Psat) of 3dBm. Then, we used those transmitter and receiver chips and demonstrated two different packaging technologies in building our mm-wave MU-MIMO arrays. We designed, fabricated, and tested tiles of 8-elements transmitters/receivers, integrated with an on-package series fed patch antennas, assembled on high-performance laminate material and on Kyocera low permittivity ceramic interposer. We illustrate the pros and cons of each packaging technology and show the superiority of the ceramic interposers for mm-wave applications and highly dense arrays.

Finally, we integrated our MU-MIMO transmitter/receiver tiles with Xilinx ZCU111 FPGA and demonstrated the world’s first mm-wave MU-MIMO arrays at 135GHz. Our transmitter MU-MIMO array has a record transmitter effective isotropic radiated power of 39dBm, a field of view of +/-15 degrees. It can support a wide range of modulation schemes (i.e., QPSK, 16QAM). The integrated transmitter and receiver MU-MIMO arrays can be used for a broad range of applications, including single beam and multibeam phased arrays, wireless backhaul, imaging, and radar applications.

The increasing data consumption due to the development in smart devices demands broadband, high-data-rate communication links both in the user end-point and backhaul links. Backhaul communication links over fiber can further be developed using optical technologies. Millimeter-wave wireless technologies can provide high data rates for both end-users and in base-stations. Millimeter-waves provide wide unlicensed and unallocated frequency bands, creating an opportunity for broadband wireless communications. At these frequencies the signal propagation range is limited and attenuation is high; but signal strength can be recovered in part by using phased arrays. In addition, short wavelengths at these frequencies allow one to place a massive number of antennas within even a small aperture, which can provide a massive number of simultaneous independent beams (multi-input multi-output: MIMO). MIMO can provide large increases in the overall system data rate.

In the first part of the dissertation, two optical phase-locked loops (OPLLs) are demonstrated. These consume 1.3 and 1.8 W of power respectively and have larger than 15 GHz locking ranges. These OPLLs were then integrated with a magnesium fluoride (MgF2) microresonator-based optical frequency comb in order to show two chip-scale optical frequency synthesizers (OFSs). This comb has a 50-dB span of 25 nm (~3 THz) around 1550 nm with a 25.7 GHz repetition rate. The optical synthesizers consume 2 and 1.7 W of power within a 10 cm^3 volume respectively. The first generation OFS achieves a tuning resolution better than 100 Hz within 5 Hz accuracy, and can switch >5 nm in wavelength in less than 200 ns by jumping over 28 comb lines.

In the second part of the dissertation, a broadband transceiver using 22 nm fully-depleted silicon on insulator (FD-SOI) complimentary-metal-oxide-semiconductor (CMOS) technology is demonstrated. The work includes transistor characterization and design of the circuit building blocks. The transmit and receive channels have more than 10 GHz 3-dB bandwidth, sufficient to support more than 10 GBaud data transmission rate. The thesis then reports transmission experiments using an earlier design generation of 140 GHz MIMO transceivers, which was fabricated in 45 nm SOI CMOS. In transmission experiments over 20 cm propagation distance in air, open eye diagrams were observed even at symbol rates as high as 8 GBaud using a 145.8 GHz carrier frequency.

We report low-cost, yet efficient printed circuit board (PCB) based off-chip antenna arrays, and IC-antenna transitions at D-Band. These are the first such reported designs working above 140 GHz. An 8-element single-row, series-fed patch antenna array shows 14 dB gain with 7 GHz bandwidth (S21). It has 9-degree E-plane and 65-degree H-plane 3-dB beamwidths. Measurement results align well with the simulations, except that the antenna resonant frequency is 4 GHz higher than design and the gain is 1-1.5 dB lower. A wirebonding transition between the transceiver ICs and antenna arrays are designed. Its performance is evaluated using 3D full electromagnetic simulations in Ansys HFSS. The transition loss is low, only about 1.8 dB, with a 10 GHz bandwidth in simulations. These simulations align well with the measurements from packaged transceivers.

Finally, a fully-packaged 4-channel MIMO receiver and a fully-packaged 2-channel transmitter are demonstrated. In wireless data transmission experiments over a 25 cm propagation distance, a single-channel transceiver using these boards shows open eye patterns up to 5 GBaud data rate using a 146.7 GHz carrier frequency. The bit-error-rate (BER) is measured at less than 10^-3 up to 2.5 GBaud data rate using the same data transmission experiment. The modules designed in this dissertation are the first fully integrated phased array ICs working above 140 GHz to the best of the author's knowledge. These modules can support multi-beam communications for the next generation of wireless communications with a massive number of beams, each providing 1-10 Gb/s, approaching 1-10 Tb/s overall data rate.

With the development of (sub) THz transistor technologies, high speed integrated circuits up to sub-THz frequencies are now feasible. These high speed and wide bandwidth ICs can improve the performance of optical components, coherent optical fiber communication, and imaging systems. In current optical systems, electrical ICs are used primarily as driving amplifiers for optical modulators, and in receiver chains including TIAs, AGCs, LPFs, ADCs and DSPs. However, there are numerous potential applications in optics using high speed ICs, and different approaches may be required for more efficient, compact and flexible optical systems.

This dissertation will discuss three different approaches for optical components and communication systems using high speed ICs: a homodyne optical phase locked loop (OPLL), a heterodyne OPLL, and a new WDM receiver architecture.

The homodyne OPLL receiver is designed for short-link optical communication systems using coherent modulation for high spectral efficiency. The phase-locked coherent receiver can recover the transmitted data without requiring complex back-end digital signal processing to recover the phase of the received optical carrier. The main components of the homodyne OPLL are a photonic IC (PIC), an electrical IC (EIC), and a loop filter. One major challenge in OPLL development is loop bandwidth; this must be of order 1 GHz in order for the loop to adequately track and suppress the phase fluctuations of the locked laser, yet a 1 GHz loop bandwidth demands small (<100 ps) propagation delays if the loop is to be stable. Monolithic integration of the high-speed loop components into one electrical and one photonic IC decreases the total loop delay. We have designed and demonstrated an OPLL with a compact size of 10 × 10 mm², stably operating with a loop bandwidth of 1.1 GHz, a loop delay of 120 ps, a pull-in time of 0.55 μs and lock time of <10 ns. The coherent receiver can receive 40 Gb/s BPSK data with a bit error rate (BER) of <10^-7, and operates up to 35 Gb/s with BER 10^-12.

The thesis also describes heterodyne OPLLs. These can be used to synthesize optical wavelengths of a broad bandwidth (optical wavelength synthesis) with narrow linewidth and with fast frequency switching. There are many applications of such narrow linewidth optical signal sources, including low phase noise mm-wave and THz-signal sources, wavelength-division-multiplexed optical transmitters, and coherent imaging and sensor systems. The heterodyne OPLL also has the same stability issues (loop delay and sensitivity) as the homodyne OPLL. In the EIC, a single sideband mixer operating using digital design principles (DSSBM) enables precisely controlled sweeping of the frequency of the locked laser, with control of the sign of the frequency offset. The loop's phase and frequency difference detector (PFD) uses digital design techniques to make the OPLL loop parameters only weakly sensitive to optical signal levels or optical or electrical component gains. The heterodyne OPLL operates stably with a loop bandwidth of 550 MHz and loop delay of <200 ps. An initial OPLL design exhibited optical frequency (wavelength) synthesis from -6 GHz to -2 GHz and from 2 GHz to 9 GHz. An improved OPLL reached frequency tuning up to 25 GHz. The homodyne OPLL exhibits -110 dBc/Hz phase noise at 10 MHz offset and -80 dBc/Hz at 5 kHz offset.

Finally, the thesis describes a new WDM receiver architecture using broadband electrical ICs. In the proposed WDM receiver, a set of received signals at different optical wavelengths are mixed against a single optical local oscillator. This mixing converts the WDM channels to electrical signals in the receiver photocurrent, with each WDM signal being converted to an RF sub-carrier of different frequency. An electrical IC then separately converts each sub-carrier signal to baseband using single-sideband mixers and quadrature local oscillators. The proposed receiver needs less complex hardware than the arrays of wavelength-sensitive receivers now used for WDM, and can readily adjust to changes in the WDM channel frequencies. The proposed WDM receiver concept was demonstrated through several system experiments. Image rejection of greater than 25 dB, adjacent channel suppression of greater than 20 dB, operation with gridless channels, and six-channel data reception at a total 15 Gb/s (2.5 Gb/s BPSK × 6-channels) were demonstrated.

This work examines the efforts pursued to extend the bandwidth of InP-based DHBTs above 1 THz. Aggressive lithographic and epitaxial scaling of key device dimensions and simultaneous reduction of contact resistivities have enabled increased RF bandwidths by reduction of device RC and transit delays. A fabrication process for forming base electrodes and base/collector mesas of highly scaled transistors has been developed that exploits superior resolution (10nm) and alignment (<30nm) of electron beam lithography. Ultra-low resistance, thermally stable base contacts are critical for extended fmax bandwidth: a novel dual-deposition base metalization technique is presented that removes contaminating lithographic processes from the formation of the base contact, thereby enabling low resistivity contacts (4 Ω-µm²) to ultra-thin base layers (20 nm). The composite base metal stack exploits an ultra-thin layer of platinum that controllably reacts with base, yielding low contact resistivity, as well as a thick refractory diffusion barrier which permits stable operation at high current densities and elevated temperatures. Reduction in emitter-base surface leakage and subsequent increase of current gain was achieved by passivating emitter-base semiconductor surfaces with conformally grown ALD Al2O3. RF bandwidth limiting parasitics associated to the perimeter of highly scaled transistors have been identified and significantly reduced, among which are high sheet resistance of base electrodes, excess undercut of emitter stripes and improperly scaled base posts. At 100nm collector thickness , the breakdown voltage of the transistor BVCEO has been increased to more than 4.1V by passivating base/collector surfaces.

With the technology improvements discussed, transistors with ft of 480 GHz and fmax in excess of 1 THz have been demonstrated at 200nm emitter width and 80nm single-sided base contact width. Transistors at the same emitter width, but 30nm base contact width exhibit ft of 550 GHz and fmax of 850 GHz. Estimations from a finite element model predict higher bandwidth on smaller footprint transistors. However, inadequacies of RF calibration structures prevent fmax extraction on these devices.