Recently, availability of big data and enormous processing power along with maturing of the applied algorithms, especially for deep learning, have led to a breakthrough in the performance of machine learning algorithms for various applications such as image classification, speech recognition, natural language processing, and so on. The rapidly growing range of machine learning applications, especially in IoT/mobile devices (smart phones, self-driving cars, virtual reality gadgets, medical devices, etc.), call for a specialized efficient neural processing platform. Of that, there is much more demand for fast, low-precision neural inference accelerators than for higher-precision systems for network training.

Though custom-designed digital accelerators significantly outperform their conventional counterparts, their performance is limited due to inherent separation of storage and computing elements and their large footprint. Analog-domain in-memory computing using nonvolatile memory (NVM) devices appears to be a promising bio-inspired solution to break the performance barrier of today's neural accelerators. Small footprint of the storage cells, and their ability to operate as multiplier-and-accumulators enable compact, fast, and energy-efficient implementation of vector-by-matrix multipliers (VMMs) as the core processing element in the neural accelerators.

In this work, we develop several compact, energy-efficient time-domain VMM approaches based on various NVM devices such as 1T1R resistive cells, 2D-NOR floating-gate devices, and 3D-NAND flash memories. In these approaches, the computation is solely performed via charge transfer while no static power is consumed in the peripheral circuitry. Moreover, the digital nature of the peripheral circuitry in these approaches significantly relaxes the technology node scaling limitation which is a serious challenge for analog-domain computing circuits. One of the key advantages of our time-domain approach is its full compatibility with complex and compact structure of the commercial 3D-NAND memory block enabling the implementation of ultra-compact mixed-signal neural operators based on this NVM platform.

In the second phase of this work, we propose “aCortex”, an extremely energy efficient, fast, compact, and versatile neuromorphic processor architecture suitable for acceleration of a wide range of neural network inference models. The most important feature of our processor is a configurable mixed-signal computing array of vector-by-matrix multiplier (VMM) blocks utilizing embedded NVM arrays for storing weight matrices. In this architecture, power-hungry analog peripheral circuitry for data integration and conversion is shared among a very large array of VMM blocks enabling efficient instant analog/time-domain VMM operation for different neural layer types with a wide range of layer specifications. This approach also maximizes the processor’s area efficiency through sharing the area-hungry high-voltage programming switching circuitry as well as the analog peripheries among a large 2D array of NVM blocks. Such compact implementation further boosts the energy efficiency via lowering the digital data transfer cost. Other unique features of aCortex include configurable chain of buffers and data buses, a simple and efficient Instruction Set Architecture (ISA) and its corresponding multi-agent controller, and a customized refresh-free embedded DRAM memory. Using aCortex estimator, we perform rigorous system-level analysis targeting various NVM devices (1T1R ReRAM, and 2D-NOR/3D-NAND flash) as well as different computing approaches (current/time mode), and propose a roadmap for the future efforts in this domain.

We propose a novel computing approach, called “Race Logic”, which utilizes a new data representation to accelerate a broad class of optimization problems, such as those solved by dynamic programming algorithms. The core idea of Race Logic is to deliberately engineer race conditions in a circuit to perform useful computation. In Race Logic, information, instead of being represented as logic levels (as is done in conventional logic), is represented as a timing delay. Computations can then be performed by observing the relative propagation times of signals injected into a configurable circuit (i.e. the outcome of races through the circuit).

In this dissertation I will introduce Race Based computation and talk about multiple VLSI implementations. We first begin by considering a synchronous approach, which uses simple clocked delay elements. Though this synchronous implementation outperforms highly optimized conventional implementations of the well-studied, DNA sequence alignment problem, its third order energy scaling with problem size and limited dynamic range of timing delays are its major pitfalls. Next, in the search for energy efficiency, we study asynchronous designs in order to understand the performance trade-offs and applicability of this new architecture. Finally, I will present the results of a prototype asynchronous Race Logic chip and demonstrate that Race-Based computations can align up to 10 million 50 symbol long DNA sequences per second, about 2-3 orders of magnitude faster than the state of the art general purpose computing systems.

The von Neumann bottleneck has been growing narrower over the years, as CPU speed and memory have been increasing much faster than the bandwidth between them can accommodate. One promising approach to circumvent this problem is logic-in-memory computing, where computation is performed in the memory itself, significantly reducing traffic between the CPU and the memory subsystem. The most practical implementation of logic-in-memory utilizes electronic devices that can perform both storage and logic while being monolithically integrated into existing CMOS technology. A very prominent example of such a device is the memristor a two-terminal memory devices with high endurance, low power consumption, and proven scalability down to 10 nm. Memristors are now actively investigated for non-volatile memory applications and energy-efficient hardware implementations of artificial neural networks. Recently, a novel logic-in-memory approach implementing material implication logic with memristors was proposed by Hewlett Packard, providing a potential new way forward for opening the von Neumann bottleneck.

The objective of this dissertation is to advance of the state of the art for material implication logic through three research goals. Our first goal was to develop a fabrication pathway for monolithical vertical integration of memristors in order to implement 3D memories. This allows us to experimentally test logic-in-memory systems. Our second goal was to determine memristor device and circuit constraints for implementing material implication logic and explore circuit and device level solutions to increase robustness of operation. Our final goal was to combine these two efforts together and demonstrate reliable material implication logic in vertically stacked memristors. To this end, we fabricated and successfully tested monolithically stacked memristive structures implemented with TiO2-based memristors. We also developed an optimized circuit configuration able to perform material implication with maximum tolerance to device variations. This allowed us to demonstrate, for the first time, hundreds of successful three-dimensional data manipulation cycles using material implication. An inter-layer NAND gate with the inputs and output in different device layers was implemented with 94% yield. This high yield demonstrates the potential for using the inter-layer stateful logic gates in larger circuits for in-memory logic. This implementation also opens the way through aggressive scaling to achieve one of the Feynman Grand Challenges - the construction of a functional nano-scale 8-bit adder in 50x50x50nm for which a circuit implementation is proposed.

The neural computation field had finally delivered on its promises in 2013 when the University of Toronto group reported a deep neural network that outperformed other machine learning approaches in image classification accuracy. That breakthrough was not due to algorithmic advances but rather the availability of high-performance graphical processors that enabled large-scale neural network modeling. Since then, the biologically-inspired neural network algorithms have become state-of-the-art approaches in many artificial intelligence tasks, and the future progress in this field hinges on even more powerful hardware. Such hardware, however, is unlikely to be implemented with the conventional digital circuit technology, whose performance seems to be saturating due to the faltering Moore’s law. On the other hand, further opportunities are presented by neuromorphic hardware that mimics critical features of biological neural networks, most importantly analog in-memory computing, in an attempt to match their energy-efficiency. Most importantly, neuromorphic hardware takes advantage of the physical-level analog implementation of vector-by-matrix multiplication (VMM), which is the most frequent operation in any neural network. The key component of such a circuit is a nanodevice with adjustable conductance —essentially an analog nonvolatile memory—used at each crosspoint of a crossbar array and mimicking the biological synapse. Prior work showed that analog VMM circuits based on redesigned eFlash memories and metal-oxide memristors, the most promising analog memory device technologies for neuromorphic computing, are much more energy-efficient as compared to the digital counterpart implemented in similar process node and performing a similar function. The main goal of this dissertation is to advance neuromorphic circuits based on memristors and eFlash memories on several fronts. The first part of the thesis is devoted to improving functional and physical performance of analog-domain vector-by-matrix multiplication with a specific focus on neuromorphic inference applications, including the development of novel programming algorithms, mitigation approaches for various device and circuit non-idealities, and design of efficient peripheral circuits. For example, we use novel programming algorithms to experimentally demonstrate <4% relative tuning error in a 64x64 passively integrated crossbar circuit despite significant variations, with 25% normalized standard deviation in device I-V characteristics. The developed post-fabrication methods for mitigating IR drops, I-V static nonlinearity, and device variations enable software-equivalent accuracy for the large-scale neural networks for the studied memristor technology. The efficacy of novel peripheral circuits is verified via SPICE modeling, which shows, e.g., POp/J-scale energy-efficiency for current-mode 55-nm NOR-flash memory circuits. The section is concluded with the discussion of our ongoing work on the design and fabrication of several large-scale neuromorphic chips. The second part of this thesis extends the work on analog VMM circuits to enable the implementation of more advanced probabilistic neuromorphic hardware, which is especially effective in solving combinatorial optimization problems. By operating the previously developed analog VMM circuit in a lower signal-to-noise-ratio regime, we achieve stochastic VMM functionality and utilize such circuits to prototype small-scale restricted Boltzmann machine and Hopfield neural network with runtime-controlled effective temperature. Furthermore, we suggest several novel hardware-friendly annealing approaches and successfully verify them by solving experimentally typical combinatorial optimization problems. The last part of this dissertation is devoted to hardware security primitives, such as physically unclonable functions and true random number generators. At the core of our idea are analog circuits based on metal-oxide memristors and eFlash memories, which are very similar to analog VMMs developed for neuromorphic computing. The main difference is that memory device non-idealities, e.g., randomness in tuning and memory I-V variations, are utilized as a rich source of static entropy, which is essential for implementing hardware security primitives. We developed three architectures - RX-PUF and VR-PUF that avoid the need for conductance tuning procedure in previously proposed memristor-based PUFs, and ChipSecure, which exploits variations in leakage current, subthreshold slope, nonlinearity, and stochastic tuning error in eFlash memory arrays to create a unique digital fingerprint. The key novelties of the proposed designs include enormous challenge-response pairs to enable strong PUF properties and a low-overhead key-booking scheme to dramatically improve the PUF reliability across a wide temperature range of operation. The analysis of the measured data in all our PUF demonstrations shows strong resilience against machine learning attacks.