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eScholarship
Open Access Publications from the University of California

Scholarly Works (4 results)

  • Thesis
  • Peer Reviewed
UC Riverside Electronic Theses and Dissertations (2010)

Analog-to-digital converter (ADC) is a very fundamental and key part to nearly all kinds of electronics. The applications cover a wide range requiring different resolution to different sampling rate, including UWB systems, radar detection, wide band radio receivers, optical communication links, CCD imaging, ultrasonic medical imaging, digital receivers, base stations, digital video (for example, HDTV), xDSL, cable modems, and fast Ethernet. Among them, lower resolution very high speed ADC is a critical part for building UWB system, disk drive read channels and optical communication.

This thesis consists of two parts. The first part focuses on the design of a high speed low resolution flash ADC in 90nm technology. Capacitive interpolation technique was used in this flash ADC in order to reduce the hardware requirement and input capacitance. No sample-and-hold (S/H) circuit is needed since the distributed capacitors (including capacitors in the very front end and the interpolated capacitors) serve to sample and hold the signals. Offset cancellation and averaging techniques are also implemented to reduce the offsets and the non-linearity. The ADC design achieves a sampling speed of 2.3GSps with 4 bits resolution in 90nm CMOS technology.

The second part describes a new comprehensive ADC design methodology for capacitive interpolated flash ADCs, aiming to provide a quantitative, yet handy design guideline for circuit designers to conduct practical ADC designs. This new ADC design methodology provides a quantitative and comprehensive mapping between ADC chip level performance specs and various design parameters at different levels, such as, interpolation factor, number of stages, pre-amplifier bandwidth, loading effects, transistor sizes, technology parameters and etc. It serves to allow IC designers to conduct quick and quantitative flash ADC designs for well-balanced overall chip performance in practices. A dynamic power consumption analysis technique for capacitive interpolated flash ADCs is also discussed.

    Cover page: High Speed ADC Design Methodology
    • Article
    • Peer Reviewed
    UCLA Previously Published Works (2016)
    Conventional on-chip electrostatic discharge (ESD) protection structures for integrated circuits (ICs) rely on in-Si p-n-junction-based devices, which have many inherent disadvantages unsuitable for ICs at nanonodes. This letter reports a novel above-IC graphene-based nanoelectromechanical system (gNEMS) transient switch ESD protection mechanism and structure. Transmission line pulse testing shows dual-polarity transient ESD switching effect with a response time down to 200 ps. This gNEMS switch is a potential ESD protection solution to realize the above-Si ESD protection designs through 3-D integration in IC back end of line.
      Cover page: A Dual-Polarity Graphene NEMS Switch ESD Protection Structure
      • Article
      • Peer Reviewed
      UCLA Previously Published Works (2016)
      We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time (tr) and duration (td) was performed across a wide temperature range ( T = -30/+110°C). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length (L), width (W), and number of graphene layers, as well as ESD pulse shapes and operation temperature.
        Cover page: Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection
        • Article
        • Peer Reviewed
        UC Riverside Previously Published Works (2021)
        The growth of the Tibetan Plateau throughout the past 66 million years has profoundly affected the Asian climate, but how this unparalleled orogenesis might have driven vegetation and plant diversity changes in eastern Asia is poorly understood. We approach this question by integrating modeling results and fossil data. We show that growth of north and northeastern Tibet affects vegetation and, crucially, plant diversity in eastern Asia by altering the monsoon system. This northern Tibetan orographic change induces a precipitation increase, especially in the dry (winter) season, resulting in a transition from deciduous broadleaf vegetation to evergreen broadleaf vegetation and plant diversity increases across southeastern Asia. Further quantifying the complexity of Tibetan orographic change is critical for understanding the finer details of Asian vegetation and plant diversity evolution.
          Cover page: Orographic evolution of northern Tibet shaped vegetation and plant diversity in eastern Asia
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