Transistor density continues to increase exponentially, but power dissipation per transistor improves only slightly with each generation of Moore's law. Given the constant chip-level power budgets, this exponentially decreases the fraction of the transistors that can be active simultaneously with each technology generation. Hence, while the area budget continues to increase exponentially, the power budget has become a first-order design constraint in current processors. In this regime, utilizing transistors to design specialized cores that optimize energy-per-computation becomes an effective approach to improve the system performance. To pursue this goal, this thesis focuses on specialized processors that reduce energy and energy-delay for general purpose computing. The focus on energy makes these specialized cores an excellent match for many of the commonly used programs that would be poor candidates for SIMD-style hardware acceleration (e.g. compression, scheduling). However, there are many challenges, such as lack of flexibility and limited computational power, that limit how effective these specialized cores are at targeting general purpose computing. Without addressing these concerns, these specialized cores would be limited in the scope of applications that they can effectively target. This thesis addresses these various challenges involved in making specialization a viable approach to optimize general-purpose computing. To this end, this thesis proposes Patchable Conservation Cores which are flexible, energy-efficient co-processors that contain the ability to be patched, enabling them to remain useful across versions of their target application. To demonstrate the effectiveness of these conservation cores in targeting a system workload, this thesis utilizes them to design a mobile application processor targeting the Android software stack. The results show that these specialized cores can cover significant fraction of the system execution while staying within a modest area budget. To further increase the fraction of the system execution that these specialized cores cover, this thesis proposes QASICs, specialized co-processors capable of executing multiple general-purpose computations. QASIC design flow exploits the similar code patterns present within and across applications to reduce redundancy across specialized cores as well as improve their computational power

The transistor density continues to increase exponentially, but the power dissipation per transistor improves only slightly with each generation of Moore’s law. Given the constant chip-level power budgets, this exponentially decreases the fraction of the transistors that can be active simultaneously with each technology generation. Hence, while the area budget continues to increase exponentially, the power budget has become a first-order design constraint in current processors. In this regime, utilizing transistors to design specialized cores that optimize energy-per-computation becomes an effective approach to improve the system performance. To trade transistors for energy efficiency in a scalable manner, we propose quasi application-specific integrated circuits, or QASICs, specialized processors capable of executing multiple general- purpose applications while providing an order-of-magnitude more energy efficiency than a general-purpose processor. The QASIC design flow is based on the insight that similar code-patterns exist across applications. Our approach seeks to exploit these similar code patterns to design specialized cores that can support many of the widely used computations. Our results demonstrate that designing relatively few QASICs can support operator functions of multiple commonly used data structures and these QASICs provide 13.5× energy savings over a general-purpose processor. On a more diverse workload consist- ing of twelve applications selected from different application do- mains (including SPECINT, Sat Solver, Vision, EEMBC, among others), our results show that QASICs reduce the required number of application-specific circuits by over 50% and the area requirement by 23% compared to the fully-specialized logic while providing energy-efficiency within 1.27X of that of fully-specialized logic. Also, at system level, our approach reduces the application energy-delay metric by 46% compared to conventional processors.

Pre-2018 CSE ID: CS2011-0964

Multi-core processors have emerged as the leading solution to the power and scalability concerns that processor designers currently face. This transition addresses microarchitectural scalability issues, but it only delays the onset of the power scalability problem. Due to limitations on threshold voltage scaling, in a few process generations, processors will only be able to make use of a small fraction of a silicon die at full frequency at once. This “utilization wall” will prevent massively multi-core processors from effectively employing more than a small subset of cores at once. If we cannot utilize the full array of homogeneous cores, then the utility of building them comes into question. This paper explores massively heterogeneous CMPs, an approach to processor design that can continue to scale performance in spite of the utilization wall. Such designs will comprise 10s to 100s to even 1000s of heterogeneous specialized processing elements (SPEs), ranging from small ASIC circuits to large speculative out-of-order general purpose processors. Massively heterogeneous CMPs combine these SPEs with an execution model that allows each part of a program to run on the SPE that can execute it most efficiently. Although the utilization wall dictates that massively heterogeneous CMPs (like all future processors) may use only a small fraction of the die at once, it uses that fraction very efficiently. This paper explores the architectural challenges that arise in designing general-purpose massively heterogeneous CMPs. Our results demonstrate that massively heterogeneous systems can extend performance scaling by realizing large gains (up to 7×) in performance and efficiency relative to more modestly heterogeneous and homogeneous designs. The paper also presents an ASIC-based SPE case study that demonstrates the ability of such systems to provide large efficiency gains even for irregular integer applications.

Pre-2018 CSE ID: CS2009-0947

Transactions have emerged as a promising way to exploit thread-level parallelism in the presence of shared data. Preventing data-races between threads traditionally implies lock-based synchronization. This comes at the risk of deadlock due to programmer error, and overly-conservative locking will limit the performance potential of parallel execution. Transactions circumvent these limitations by detecting and serializing data dependencies between threads at runtime without the need for locks. Hardware supported transactional memory builds on top of the cache coherence mechanism of shared memory multi-processors to detect data dependence conflicts between concurrent transactions. Recent proposals address the need to support the virtualization of transactions when the finite capacity of the cache is exceeded. These techniques have either a fast commit or abort, but not both. Similarly they support either fast conflict detection but are not able to handle swapped processes, or slow but complete. In this paper we examine page-based transactional memory to provide virtual transactions. We combine transaction bookkeeping with page address translation for fast conflict detection with fast access of overflowed transactional data. Our approach provides fast virtual transaction commit and abort, and conflict detection. We provide quantitative measurement of performance, whereas most examinations of virtualized transaction techniques provide only theoretical analysis of performance.

Pre-2018 CSE ID: CS2005-0848