In recent times, even small improvements in performance and power are seen as huge wins in digital integrated circuit (IC) design. In advanced technology nodes, design of energy-efficient chips with high yields faces many challenges. Notably, aspects of interconnect design are now among the most significant challenges to obtaining ICs with low power, high performance and high yield. This thesis presents new techniques to (i) improve the construction of interconnects, (ii) improve the estimation of wirelengths of interconnects given a placement, and (iii) improve manufacturing yield by eliminating imbalance of metal layer usage in interconnects used for clock distribution.

This thesis has three main contributions, presented in the three main chapters. First, this thesis presents two tree construction algorithms for simultaneous improvement of wirelengths and source-to-sink pathlengths of routing trees. Second, this thesis defines a new property of placed signal nets and the corresponding pin locations, and proposes an improved lookup table to accurately estimate wirelengths of these nets. Finally, this thesis presents a technique to improve yield of ICs by layer-balancing the clock paths of each launch-capture register-pair in the design.