In recent decades, the semiconductor industry has experienced a substantial revolution driven by the adherence to Moore’s Law. As gate counts have surged into the tens of billions, the impact of physical design methodology on integrated circuit (IC) manufacturing has expanded across various applications, including artificial intelligence (AI), automotive communication, virtual reality (VR) and mobile system-on-chip (SoC). Additionally, with continued technology scaling, the complexity of design rules has increased due to the stochastic impacts of extreme ultraviolet lithography (EUV) during the semiconductor manufacturing stages. Meeting specified targets for power, performance, area and cost (PPAC) necessitates consideration of both intricate design rules and the scale of billions of transistors. This introduces challenges for physical design flows within electronic design automation (EDA) tools. An overarching challenge pertains to research infrastructure: many EDA research infrastructures come with limitations related to licensing, which restricts access and usability across academia and industry. As a result, researchers often find themselves manually integrating physical design flows from various tools, introducing an additional layer of complexity to the semiconductor engineering process.

This thesis introduces robust physical design methodologies and open-sourced and centralized EDA infrastructures, along with their applications. The contribution of this thesis fall into three main categories: (i) general physical design methodologies, (ii) technology-aware physical design methodologies, and (iii) open-sourced and centralized EDA infrastructure.

To address challenges in general physical design flow, this thesis presents two works:(i) On the Superiority of Modularity-Based Clustering for Determining Placement-Relevant Clusters and (ii) A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop.

To address challenges specific to advanced technology nodes, this thesis presents two works:(i) CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation and (ii) SLO-ECO: Single-Line-Open Aware ECO Detailed Placement and Detailed Routing Co-Optimization.

Finally, to address challenges in the limited EDA infrastructure, this thesis presents:RosettaStone: Connecting the Past, Present and Future of Physical Design Research.