Data movement has become a limiting factor in terms of performance, power consumption, and scalability of high-performance compute nodes with increasing numbers of processor and memory systems. Optical interconnects enabled by Silicon Photonics could not only overcome this limitation but also change the way we think about system architectures and memory hierarchies. This dissertation aims to introduce and evaluate scalable high performance computing architectures based on optical interconnects. This dissertation presents the motivation and background, architecture design, and evaluation results for the following case studies:Investigating the design challenges in large-scale many-core processors, the impact of interconnection fabric on the overall system performance and power consumption, and how Silicon Photonics can alleviate system constraints. Studying on-chip memory networks capable of providing HPC compute nodes with terabytes of memory capacity by interconnecting several 3D stacked DRAM modules through a packet-switched network interface. Replacing legacy interconnects with sophisticated optical networks could significantly reduce memory access time and energy - a largely unexplored research area. Addressing the scaling limitations in chiplet-based systems, in particular, large inter-chiplet non-uniform latencies, distance-related energy overheads, and limited Input-Output (IO) bandwidth, and exploiting the properties of optical interconnects to propose a scalable uniform memory architecture. Rethinking the architecture of state-of-the-art high-throughput accelerators, the impact of memory access latency variations on the overall performance and system design, and the key challenges in scaling memory and compute capacity in these systems. A new architecture is proposed to reduce the contention within the memory system with the help of a partitioned memory controller and an all-to-all passive optical interconnect that is amenable for a 2.5D based implementation using off-the-shelf memory modules.

The explosive growth of the data traffic in today's high performance computing (HPC) and datacenter systems demands massive-scale and energy-efficient data interconnections. On the manufacturing side, as the lithography reaches atomic scale and fabrication costs continue to rise, Moore's law is barely maintaining its trend of continuing increases in transistor densities so that electrical integrated circuits (ICs) alone are reaching its bottleneck. Optical interconnects on silicon photonic (SiPh) platform is an attractive solution due to the capabilities of transmitting data at the speed of light without having a length-dependent impedance. On the architecture side, today's datacenters heavily rely on cascaded stages of many power-hungry electronic packet switches interconnected with a fixed networking topology. The fixed topology cannot dynamically adapt the bandwidth to the varied traffic patterns, which prevents better utilization of computing resources. Optical wavelength-and-space selective switching fabrics is a particularly suitable solution due to the ability of dynamic configuration and reconfiguration in both spectral and spatial domains. On the other hand, neuromorphic computing have gained growing popularity compared with traditional von Neumann computing due to its superior performance in various tasks such as computer vision, speech recognition, machine translations, medical diagnoses, and the game of Go. Photonic neural networks (PNNs) consisting of synaptic interconnections and neurons with nonlinear activation functions can improve both energy efficiency and throughput significantly compared with electronic artificial neural networks (ANNs). Recently, one crucial piece of research is focused on implementing high radix (e.g., 1024×1024) photonic synaptic interconnections.This dissertation firstly presents the demonstration of arrayed waveguide grating router (AWGR)-based all-to-all optical interconnects using silicon photonic low-latency interconnect optical network switch (Si-LIONS). The impact of intra-band crosstalk on scalability is investigated and experimentally verified. An 8×8 chip-scale Si-LIONS system with integrated silicon nitride (SiN) AWGR and SiPh transceivers are taped out and fabricated by foundry multi-project-wafer (MPW) run. Wavelength routing functionality is demonstrated with error-free data transmission at 10 Gb/s using the on-chip modulators and SiN AWGRs. A 64×64 wavelength routing Thin-CLOS system with significantly improved scalability is also experimentally demonstrated in a 1U rack enclosure. Second, the dissertation proposes a bandwidth-reconfigurable SiPh switching fabric called Flex-LIONS (Flexible Low-Latency Interconnect Optical Network Switch). Flex-LIONS architecture is enabled by combining an AWGR-based all-to-all interconnection, microring resonator (MRR) add-drop filters, and multi-wavelength spatial switches. Flex-LIONS exhibits 21× fewer number of switching elements and 2.9× lower on-chip optical losses for 64 ports than the state-of-the-art architectures. A multi-free-spectral-range (FSR) integrated 8×8 SiPh Flex-LIONS module has been designed, fabricated, and packaged. Successful system testing demonstrates error-free all-to-all interconnects for both FSR0 and FSR1 with a 5.3-dB power penalty induced by AWGR intra-band crosstalk under the worst-case polarization scenario. After reconfiguration in FSR1, the bandwidth between the selected pair of nodes is increased from 50 to 125 Gb/s while maintaining a 25 Gb/s/λ all-to-all interconnectivity in FSR0. The design, layout, and fabrication of an O-band 16×16 SiPh Flex-LIONS chip with ns switching speed are also presented. Third, the dissertation proposes a PNN architecture based on tensor-train decomposed synaptic interconnections. The device implementation design shows that high-radix (1024×1024) synaptic interconnections can be enabled by cascaded small-radix (16×16) photonic tensor-train cores. At 1024×1024, the proposed tensorized PNNs reduce the insertion loss by 171.8 dB and the number of Mach-Zehnder interferometers (MZIs) by 582× compared with conventional PNNs. In the end, the design, layout, and fabrication process development of transfer-printed III-V-on-Si quantum dot (QD) lasers are presented. Also, chirp-free optical in-phase-quadrature (IQ) modulators based on injection-locked VCSEL phase array are experimentally demonstrated. 20-GBd BPSK signal is synthesized with a peak-to-peak drive voltage of only 400 mV. Nyquist pulse shaped drive signals at 10, 30, and 40 GBd indicates the modulator's chirp-free operation by showing the flat top of the optical spectrum.

ABSTRACTOptical phased arrays (OPAs), by controlling the phase and/or amplitude of optical emitter structure (e.g., grating coupler, 45-degree vertical coupler), have been widely used in applications such as light detection and ranging (LIDAR), imaging, and free-space communication systems. OPAs in the mid-wave infrared (MWIR) and long-wave infrared (LWIR) regime, therefore, will be a good candidate for realizing thermal or gas-sensing, LIDAR with a lower level of turbulence. Here, based on our previous work, we propose an integrated non-mechanical OPAs-based beam steering system using a germanium-silicon optical platform. In the functional device part, we utilize vertical germanium via emitter and grating emitter arrays at MWIR and LWIR, respectively. Also, considering the fabrication complexity, we are now demonstrating a phase-change-material (PCM) assisted grating emitter to realize MWIR beam steering. Besides, we collaborated with AIM Photonics, demonstrating a large-scale lateral emitter array by foundry-based fabrication. For the light source part, Quantum Cascade Lasers (QCLs) are the only electrically pumped semiconductor light sources that can operate at room temperature over the entire MWIR/LWIR spectral range. We collaborate with other research groups and a commercial company to grow QCL wafers We design the III-V material QCL laser integration part with the germanium-silicon platform, to guarantee the good mode transition between III-V mesa and germanium waveguide. The integrated process will rely on the emerging micro-transfer-printing technology. We have already made some testing preparation work for this fabrication process.

Optical communication systems are being widely deployed all around the world. One ofthe key techniques behind all these properties is wavelength division multiplexing/demultiplexing (WDM) [1]. To implement WDM systems in photonic integrated circuits, arrayed waveguide grating (AWG) plays an important role as the core device doing both the demultiplexing and routing functions of wavelength channels [2]. The working principles of AWG are discussed in detail in Chapter 2. Based on these properties, the workflow of determining all the geometric parameters needed for designing a low-loss functional AWG is presented in the second section in Chapter 2. To have an accurate estimation of the performance of the AWG being designed, the last section in Chapter 2 presents the flowchart showing how to build a fast and accurate AWG simulator using Gaussian approximation, Fourier Transform, and mode coupling theory. Apart from basic theories of AWG design, examples including traditional AWG router (AWGR) and some other fancy photonic integrated devices such as flat-top AWG, reflective AWG/AWGR, polarization-insensitive AWG are discussed in depth in Chapter 3. In Chapter 4, fabrication processes of SiN-based waveguide platform and measurement results of regular AWGs and reflective AWGs are described in detail. In Chapter 5, sophisticated system-level applications using AWGs including optical arbitrary waveform generator (OAWG), optical synaptic interconnections, and a passive part of WDM laser are introduced.

Photonic integrated circuits (PICs) are widely used in various applications, such as optical sensing, computing, and communication, thanks to the development of multiple photonic components, including light sources, waveguides, couplers, splitters, combiners, multiplexers, detectors, and modulators. Many material platforms can be employed for PICs. Silicon photonics taking advantage of the mature complementary metal-oxide-semiconductor (CMOS) fabrication technology stands out as a good choice. Silicon-on-insulator (SOI) platform is attracting more interest since it is CMOS compatible, cheap, and scalable. Silicon nitride (Si3N4) platform is also CMOS compatible and can be a supplementary and substitution of the Si platform in some cases, especially when low propagation and high scalability are required. Complex integrated photonics systems usually require the integration of many platforms.The explosive growth of the demands for sensing and data transferring drives the development of integrated photonics. For example, future autonomous vehicles require low-cost, high-performance light detection and ranging (LIDAR) systems. Optical interconnects are proposed and being explored for modern high-performance computing (HPC) systems. Modern astronomy needs a small size, weight, and power consumption optical sensing system to significantly reduce the cost. Integrated photonics are continuously being explored and developed for higher performance and lower cost. This dissertation presents the development of PICs for optical imaging and communication. Chapter 1 introduces integrated photonics and briefly introduces all the works in this dissertation. Chapter 2 presents our multi-layer Si3N4 platform, including the device design, simulation, fabrication, and measurement. This chapter experimentally demonstrates our multi-layer Si3N4 platform. Chapter 3 proposed and demonstrated a low-loss and broadband optical interposer for large-scale integration. The interposer includes low-loss inter-chip couplers and can be extended to a wafer scale, which shows great potential for large-scale heterogeneous integration for modern sensing and communication systems. Chapters 4 and 5 discuss the segmented planar imaging detector for electro-optic reconnaissance (SPIDER) realized by PICs for astronomy. The SPIDER uses interferometric imaging based on PICs and can significantly reduce the size, weight, and power consumption compared to traditional bulk optical devices. Chapter 4 presents a SPIDER imager formed by many chips and a high-resolution SPIDER imaging achieved using a wafer-scale fabrication technique. Chapter 5 presents a surface-coupled SPIDER imager based on a broadband surface coupler. Chapter 6 investigates the PICs for an elastic RF-optical network. The PICs are based on our multi-layer Si3N4 platform and include arrayed waveguide grating (AWG), multi-mode interferometer (MMI), and thermal phase shifters. The PICs show the capability of generating optical signals for RF-beam forming. Chapter 7 summarizes the dissertation.

Three-dimensional (3D) photonic packaging is a pivotal technology for integrating photonics components into compact and efficient optical systems. This dissertation presents advanced techniques for achieving cutting-edge 3D packaging, such as ultrafast laser inscription (ULI), optical phased arrays (OPAs), and metalenses. In ULI, we successfully demonstrated arbitrary vertical ULI waveguides within Eagle glass and an optical interposer, achieving a 0.62 dB/cm propagation loss. Further advancements led to a record-low loss of 0.16 dB/cm using germanium-oxide doped glass. We also employed a waveguide routing tool to demonstrate a 3D fan-in/fan-out device for multi-core fiber integration with SMF-28 fiber arrays. Furthermore, we presented a first 3D arrayed waveguide grating router (AWGR) operating at 1550 nm, created through ULI. Leveraging a multi-scan technique, we achieved a 399.1 GHz channel spacing, and a 2.02 nm 3 dB-passband. The integration of the AWGR with a fan-in/fan-out structure shows its versatility in 3D photonic integration. In optical beam steering, we developed a near-infrared (NIR) OPA with a 5 mm emitting area and 1.3 μm waveguide pitch, exhibiting 3.3° axial and over 40° lateral steering. Additionally, a mid-wave infrared (MWIR) OPA based on a germanium-silicon photonic platform achieved remarkable results, including 0.18° axial and 12.7° lateral beam steering. Furthermore, a commercial foundry was employed to fabricate 64 × 64 OPAs with integrated transistors, operating at wavelengths of 3.8 μm and 4.6 μm. For metalenses, we developed polarization-diversifying highly-dispersive metalenses tailored for four spectral bands (0.76 μm, 1.61 μm, 2.06 μm, and 2.32 μm) to enable compressive hyperspectral imaging. These metalenses with a 20 mm diameter boast impressive spectral resolving powers (10000, 5000, 4000, and 3571, respectively). Initial tests on a 2 mm metalens designed for a 2.06 μm wavelength validated its focusing capabilities, achieving a 46 % transmission efficiency. Additionally, the off-axis metalens displayed clear polarization splitting and a 12 μm focal spot shift during a 2 nm wavelength tuning.

The fast development of Photonic Integrated Circuits (PICs) has led to advances not only in the fundamental elements (such as ultra-low loss waveguide platforms and arrayed waveguide gratings (AWGs)) but also in the functionalities including large-scale optical interconnects, miniaturized imaging systems, low-loss and wide bandwidth communication transceivers, and precision metrology. A complete design/simulation, fabrication, and characterization routine is demonstrated on the ultra-low-loss multi-layer Si3N4 waveguide platforms in addition to the standard III-V and SOI PIC platforms, offering the superior performance of flexibility in the vertical integration and of minimizing the system throughput loss.To catch up with the needs and expectations from the modern wavelength division multiplexing (WDM) communication infrastructure, AWGs stand out of its alternatives (cascaded Mach-Zehnder Interferometer lattice filter and Echelle gratings) in the finite impulse response (FIR) multiplexers (MUXs) and demultiplexers (DEMUXs) categories with better performance on the device crosstalk level, insertion loss, and device footprint. A concise and comprehensive AWGs modelling and simulation routine based on Fourier optics is presented. I will introduce the modelling and characterization results of both standard Gaussian and flat-top AWGs on the developed Si3N4 waveguide platform with capabilities as MUXs and wavelength routers in the optical communication O and C band as the building blocks for complex PICs. I will present the new generation PICs based on our proposed Segmented Planar Imaging Detector for Electro-optical Reconnaissance (SPIDER) for a small-scale interferometric imaging system, relying on the sampling in the spatial Fourier domain via multiple baselines in PICs for an image reconstruction offline. The Si3N4 PIC contains path-length matching waveguides, large channel spacing AWGs as DEMUXs, multimode interferometers (MMI), and phase tuning sections. Thorough characterization and study of the PIC performance are carried out, and the sustainability of the PIC for Low Earth Orbit (LEO) mission is confirmed. In the end, I will propose and show novel and compact prism-waveguide couplers utilizing the evanescent wave coupling phenomenon together with mode size converter (negatively-tapered waveguide) for the efficient on-chip coupling towards the low-index (fluoride compounds) ultra-high-Q resonators for the first time. Thus, it paves the way towards the fully monolithic integrated optical frequency comb (OFC) sources for practical applications in optical communications, precision navigation, and optical sensing.

Various types of memory devices have been investigated for the development of next-generation memory technology with high operating speed, high reliability, and low leakage currents. Thyristor Random Access Memory (TRAM) can be one of the most promising candidates. In this work, we demonstrate the memory operation characteristics of TRAM with measurement and simulation results. The results have shown non-volatile characteristics while holding voltage applied. The holding voltage is required voltage condition to keep charges stored in memory. TRAM also has shown high speed switching operation with device PNPN structure. However, the conventional TRAM with two terminal designs has some disadvantages such as short retention time and large leakage currents. Additionally, the PNPN device structure has shown difficulties in controlling the current flows. Therefore, we propose a Three-Terminal TRAM (3T-TRAM) design and compare the device performance with the conventional Two-Terminal TRAM (2T-TRAM). The proposed 3T-TRAM has an additional gate contact to control the currents flow, which makes low leakage currents and high retention characteristics. The optimized design with different doping conditions has been investigated. With the optimized design, we can expect that 3T-TRAM can replace current dynamic random-access memory (DRAM) with excellent performance and be applied as a next-generation high speed computing memory.

Neuromorphic computing utilizes the computing method of the human brain to providesolutions to artificial intelligence. Developing Neuromorphic computing hardware is crucial to closely emulate how the human brain works. Spiking neural networks (SNN) is a kind of neuromorphic computing that provides a new computational paradigm capable of highly parallelized, real-time processing. Photonic spiking neural networks (PSNNs) potentially offer exceptionally low loss, low power, highly parallel, and high throughput compared to their electronic neuromorphic counterparts while maintaining their benefits in terms of event-driven computing capability. This thesis presents PSNN hardware utilizing monolithic silicon photonics (SiPh) process designs which consist of a Mach-Zehnder Interferometric (MZI) mesh incoherent network and event-driven laser optoelectronic spiking neurons. The Izhikevich-inspired optoelectronic spiking neuron consists of two photodetectors for excitatory and inhibitory optical spiking inputs, electrical transistors’ circuits providing spiking nonlinearity, and a laser for optical spiking outputs. There are two designs of optoelectronic spiking neurons demonstrated in the Section 2 and Section 3, respectively. One design focusing on the pursuit of energy efficiency (energy-efficient neuron) and another one focusing on the heterogeneity of neuron dynamics (heterogeneous neuron). Both event-driven neuron designs are inspired by the Izhikevich model incorporating both excitatory and inhibitory optical spiking inputs and producing optical spiking outputs accordingly. The neuron models are verified in Verilog- A and simulated the circuit-level operation of various cases with excitatory input and inhibitory input signals. The experimental results closely resemble the simulated results and demonstrate how the excitatory inputs trigger the optical spiking outputs while the inhibitory inputs suppress the outputs. Section 4 demonstrated a variation of the Random Backpropagation (RPB) learning algorithm on the MZI mesh synaptic interconnects and matched the performance of a standard linear regression on a simple classification task. The MZI mesh synaptic interconnects also connected with the heterogeneous neuron design in Section 3 to show the result of 89.3% accuracy on Iris image classification. The scenarios of multi-layer PSNN hardware packaging are also presented for future large-scale neuromorphic computing hardware. Section 5 presents the future direction for both energy-efficient neuron and heterogeneous neuron, which implemented with advanced transistor technology and show the benchmarking results. The nano energy-efficient neuron can achieve an estimated 21.09 fJ/spike input that can trigger the output from on-chip nanolasers running at a maximum of 10 Gspike/second in the neural network. Utilizing the simulated neuron model, the simulation results show 90% accuracy on unsupervised learning and 97% accuracy on a supervised modified FC neural network. The benchmark shows the PSNN design can achieve 50 TOP/J energy efficiency, which corresponds to 100x throughputs and 1000x energy-efficiency improvements compared to state-of-the-art electrical neuromorphic hardware such as Loihi and NeuroGrid. The nano heterogeneous neuron has power consumption of 1.18 pJ/spike output, and is predicted to achieve 36.84 fJ/spike output with a 7 nm CMOS platform (e.g. ASAP7) integrated with silicon photonics containing on-chip micron-scale lasers.

We demonstrate an error-free four-user 10-Gb/s/user optical code-division multiple-access network testbed employing the spectral phase encoded time spreading technique and nonlinear thresholding. The experiments successfully overcome multiuser interference, resulting in error-free operation.