Skip to main content
Open Access Publications from the University of California

Top-down modeling of RISC processors in VHDL


In this report, we present a top-down VHDL modeling technique which consists of two main modeling levels: specification level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and effectiveness of this methodology. All models have been simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibilty of the modeling strategy and provide performance measures of RP design features.

Main Content
For improved accessibility of PDF content, download the file to your device.
Current View