Estimation of schedules for control/datapath pipelining
Scheduling estimation in system level design plays an important role in estimating design metrics of a hardware implementation. Moreover, accurate estimates based on a realistic design model are usually expected. In this report, we present techniques for scheduling estimations based on a control/datapath pipelining architecture. Schedules are computed under both resource and architectural constraints. The resource allocation includes not only functional units but also storage and communication units. Our techniques enable designers to obtain fast and accurate estimates of scheduling.