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Way Stealing: A unified data cache and architecturally visible storage for instruction set extensions

  • Author(s): Kluter, T
  • Brisk, P
  • Charbon, E
  • Ienne, P
  • et al.

Published Web Location

http://www1.cs.ucr.edu/faculty/philip/papers/journals/tvlsi/tvlsi13-waystealing.pdf
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Abstract

Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offers higher bandwidth than interfacing the ISEs the processor's register file, and eliminates the need to allocate separate memories called architecturally visible storage (AVS) that are dedicated to the ISEs, and to ensure coherence between the AVS memories and the processor's data cache. Our results show that Way Stealing is competitive in terms of performance and energy consumption with other techniques that use AVS memories in conjunction with a data cache. © 1993-2012 IEEE.

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