UC Santa Cruz

The NAND technology has become a popular research area and implementation choice due to its non-volatile flash memory characteristics. There are many engineering challenges when it comes to NAND technology. Some of the limiting factors are reducing the transistor width and increasing read and write performance. The device physics for NAND floating gate cell technology also introduces challenges. Using a floating gate transistor that can address up to 4 bits per cell allows for higher density. However, this introduces a higher internal current leakage that can cause read and program inaccuracies. With floating-gate 3D NAND technology, we are able to better the data retention and have better QLC (Quad-Level Cell) capability. 3D NAND technology has a series of memory cells interconnected that can achieve higher data density and increased storage capacity. In this research, the Gen-4 NAND Flash device functionality is explored by design validation to achieve higher solid-state drive performance. This technology is 144-Layer QLC NAND Flash which is 1024Gb in density. My contributions are implemented showing improved read and write performance for customer operations and how inaccuracies are dealt with from a software and hardware perspective. Silicon wafer testing is also explored to fully characterize and analyze the problem.